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SPI_VHDL
- SPI串口的内核实现(vhdl),可以用qII等软件直接加到FPGA或者CPLD里面.-the SPI Serial Kernel (vhdl) can be used directly qII software foisted CPLD or FPGA inside.
vhdl-多功能电子表
- 这是一个用vhdl编的多功能电子秒表,可以记录几个人的时间,并且可以在跑秒的时候查看记录。。〔原创〕-This is a series with VHDL multifunctional electronic stopwatch, can be recorded by several people, and that they could run in the second examined the records. . [Original]
pinlvji 频率计VHDL编程
- 频率计VHDL编程。设计一个4位数字显示的十进制频率计,其测量范围为1MHz,测量值通过4个数码管显示以8421BCD码形式输出,可通过开关实现量程控制,量程分10kHz、100kHz、1MHz三档(最大读数分别为9.999kHz、99.99kHz、999.9kHz); 当输入信号的频率大于相应量程时,有溢出显示。 -Cymometer VHDL programming. Design of a 4-digit decimal display frequency, the measu
基于vhdl的二进制转BCD码的设计
- 基于vhdl的二进制转BCD码的设计,已经经过调试,可直接使用,Vhdl based on binary code to BCD design, has been testing can be used directly
THS5651是一款高速DA转换器
- THS5651是一款高速DA转换器,最高转换频率可到达100MBPS,该程序利用VHDL语言对THS5651进行控制,THS5651 is a high-speed DA converter, the maximum conversion frequency can be arrived at 100MBPS, the use of VHDL language in the process control of the THS5651
masplus-works 用VHDL语言编写的八进制计数器
- 用VHDL语言编写的八进制计数器,在MASPLUS环境下编译通过,可直接使用。-Octal counter using VHDL language, compiled by MASPLUS environment can be used directly.
ug_virtual_jtag_design_example 包含两的关于Virtual JTAG的应用实例
- 包含两的关于Virtual JTAG的应用实例,可以为Virtual JTAG操作提供借鉴。,Contains two Virtual JTAG on the application, can provide reference Virtual JTAG operation.
learn_dds.基于quartus ii 9.0的简易dds波形发生器
- 基于quartus ii 9.0的简易dds波形发生器,可以产生正弦,方波,三角波,可变幅,可变频。非常适合学习使用,使用时请按自己的芯片和引脚设置,Quartus ii 9.0 Based on dds simple waveform generator can produce sine, square, triangle wave can be amplitude, frequency can be. Very suitable for learning to use, when used
shift_register.用Verilog实现的移位寄存器
- 用Verilog实现的移位寄存器,可以实现左移、右移等功能,Using Verilog implementation of the shift register, you can achieve the left, shifted to right and other functions
add(FLP).32位元的浮点数加法器
- 一个32位元的浮点数加法器,可将两IEEE 754格式内的值进行相加,A 32-bit floating-point adder can be both within the IEEE 754 format to add value
FFT-IP.介绍了基于FPGA的FFT实现方法
- 介绍了基于FPGA的FFT实现方法,并给出了实例程序,程序通过验证,可以直接使用,FPGA based on the realization of the FFT method, and gives examples of procedures, procedures for the adoption of authentication, can be directly used
miaobiao 用verilog VHDL描写的秒表程序
- 用verilog VHDL描写的秒表程序,可以显示百分秒,秒和分。-Verilog VHDL with the descr iption of a stopwatch program, can display the arc, seconds and points.
同有SPI接口的器件进行通信对SPI接口器件的读写控制vhdl源程序
- vhdl实现spi可以同有SPI接口的器件进行通信对SPI接口器件的读写控制vhdl源程序,fpga cpld-vhdl spi can achieve devices with a SPI interface to communicate with devices on the SPI interface to read and write vhdl source code control
Viterbi_IP.rar
- viterbi译码器的IP核,可以直接编译使用,viterbi decoder IP core, the compiler can directly use
stopwatch.rar
- 秒表可计时,用VHDL编译的源代码,从0.1到60秒计时,解压后直接用Quartus打开project即可,Stopwatch timer can be used to compile the VHDL source code, from 0.1 to 60 seconds from time, after extracting the direct use of Quartus can open the project
Source.rar
- PWM Verilog源代码,可以通过仿真测试,PWM Verilog source code, can be tested through simulation
bpsk1.rar
- 介绍qpsk调制的代码!初学者可以参考参考!比较简单.,Introduction QPSK modulation code! Beginners can refer to reference! Relatively simple.
dianziqing.rar
- vhdl代码: 电子琴程序设计与仿真!初学fpga者可以参考参考!!比较简单,VHDL code: program design and simulation of electric piano! FPGA beginner who can refer to reference! ! Relatively simple
USB.rar
- 用VHDL实现的USB IP核,大家可以参考下,Use VHDL to achieve USB IP core, we can refer to the following
MICO8_DEMO_03_18_08.ZIP
- Lattice 超精简8位软核CPU--Mico8,开放所有源代码,包括VHDL,编译器,支持GCC编译器。可在Lattice所有FPGA和MachXO 器件上使用。本例包含示例和说明文档。对使用Lattice器件的用户或者学习CPU设计的人员有较高参考价值。,Lattice super-streamlined eight soft-core CPU- Mico8, open up all the source code, including VHDL, the compiler to supp