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pinglvhecheng
- 程序用VHDL实现: 频率合成,DDS 主要调用LPM-procedures using VHDL : frequency synthesis, DDS major call LPM
ddsall
- DDS的vhdl语言源程序实现 该程序可实现1HZ频率步进-DDS source VHDL language to achieve the program can be realized 1HZ frequency Step
ddsVHDL
- 基于VHDL的DDS设计,在QUTURS2zhon仿真通过-based on the DDS VHDL design and simulation through the QUTURS2zhon
ddfs
- 我自己用vhdl实现编的dds,能实现正弦波,方波,三角波。-my own use VHDL to achieve series dds, able sine, square, triangle wave.
dds_quicklogic
- 高手写的VHDL源码,实现DDS跳频器功能 请大家多提意见-experts write VHDL source code, the frequency-hopping DDS functionality Please speak up
ddsmatlab
- dds在dspbuilder下产生VHDL源码及其测试激励文件的matlab模型,在modelsim下仿真通过-dds dspbuilder under the VHDL source code and test incentives document matl ab model, the simulation under through modelsim
2006-9-21PanWeicaiDDS
- 这是一个DDS程序,用VHDL编写,实现的是一个频率可调的方波-This is a DDS procedures, using VHDL prepared achieve is a frequency adjustable square
GetRomData
- 生成4种方式的DDS输出的读表程序的VHDL源代码程序。-four ways generation of DDS output of the meter reading procedures VHDL source code procedures.
ddssheji
- 这是用VHDL语言编写的一个DDS频率合成器的源程序-VHDL prepared a DDS DDS source
EXPT12_10_PHAS_PLL1
- VHDL 实现DDS的数字移相信号发生器的设计代码.直接解压打开就可以运行..自己写的代码-VHDL shifter DDS signal generator design code. Directly extract can run on open .. write their own code
DDSsingal
- 三相直接数字频率合成器dds的VHDL源码,希望对大家有帮助-three-phase direct digital frequency synthesizers dds VHDL source code, we hope to help
ddsproject
- 用VHDL进行的dds系统设计,包括键盘输入和LCD显示,编译通过了
DDS
- 基于FPGA的用VHdl硬件语言实现的直接数字合成(DDS)。-FPGA hardware with VHdl of DDS-based language.
DDS
- DDS的FPGA实现(VHDL),只可调频,调幅可于外部DA实现。(内附三角波、正弦波、方波的rom调用)-DDS on FPGA (VHDL), only FM, AM can be implemented in an external DA. (With triangular wave, sine wave, square wave rom call)
DDS
- FPGA,ISE12.2,DDS代码,VHDL语言-FPGA, ISE12.2, DDS the code, VHDL language
DDS-VHDL
- 数字频率计DDS的VHDL代码,有很详细的注释-the source code of DDS in VHDL
ZHWX
- DDS 产生正弦信号,OOK,AM三种波形。 使用xilinx FPGA VHDL-DDS. Resulting in sinusoidal signal, OOK, AM three waveforms. Using xilinx FPGA VHDL.
dds
- 用VHDL语言实现的dds信号的源代码,已测验,可通过-dds in vhdl
src
- 初始化DDS模块,使能正线性扫频,参数化设置(DDS code VHDL parameter setting)
DDS
- DDS FPGA Verilog vhdl