搜索资源列表
LCD-display
- fpga的键盘阵列LCD显示程序，包括vhdl文件，顶层文件和工程文件-fpga array of keyboard LCD display procedures, including vhdl files, top-level files and project files
ADSP2011Local
- pci9054芯片本地总线控制示例程序，可用于pci驱动和应用程序的测试。每隔一段时间产生一次中断，产生1，2，3等递增数据，配合pci9054驱动和应用程序完成数据传输 2.说明：文件夹内是Quartus 9.0的工程文件，使用Verilog语言。-pci9054 local bus control chip sample program can be used for pci driver and application testing. Generate an interrupt at r
VHDL-Project
- Design of a Moore Synchronous Sequential Machine that operates according to the following two sequences.
adfmreceiver
- The design of the All Digital FM Receiver circuit in this project uses Phase Locked Loop (PLL) as the main core. The task of the PLL is to maintain coherence between the input (modulated) signal frequency,iωand the respective output frequency,oωvia p
working_code
- rs 485 working code for project
vhdl
- 基于vhdl的串行扫描显示电路设计，打开工程文件就可实现，并提供下载文件。-Vhdl serial scan based circuit design, open the project file can be achieved and provides download the file.
project
- It provides the code of or and decoder24 and encoder42 in VHDL language
VHDL
- 基于FPGA的IIR滤波器的各模块VHDL程序- such as in science and project technique. Compared with FIR digital filter, IIR digital filter can get high selectivity with low factorial.
Verilog-Niosii-TLC1549
- niosii的一个完整的工程 Q2 软件是9.1版本，里面做了一个TLC1549的AD转换串转并的模块-niosii project with a TLC1549 module
TrafficLight
- VHDL开发的数字交通灯控制器，项目实训内容；-The development of digital traffic light controller VHDL, project training content
dc3and8
- 3-8译码器VHDL工程源代码，含工程、VHDL源码、下载文件等-3-8 decoder VHDL project sourcecode
counter
- this source is a counter vhdl project :)
ProjectLoto
- VHDL Project for a loto application
cnt4
- 4-bit counter (VHDL project)
Project
- 基于VHDL语言编程实现了十字路口的交通灯控制器-Based on VHDL language programming realized the intersection of traffic light controller
VHDL
- VHDL应用编程实例,收录部分例程可供做项目时作为参考.-VHDL application programming examples, a collection of some of the routines available to do the project as a reference.
vhdl-clock-with-vga-output-for-Nexys-2
- Vhdl code for a working digital clock which can be displayed on a vga screen. The clock can be set using a single pushbutton. This project was written for nexys 2 board but can be easily ported to any other fpga using vhdl.
HDMI
- HDMI 接收端模数混合设计方法 pdf 论文 -HDMI recevice analog design pdf project
assigment3
- Construct VHDL models for 74-139 dual 2-to-4-line decoders using three descr iption styles, i.e., behavioral, dataflow and structural descr iptions. Synthesize and simulate these models respectively in the environment of Xilinx ISE with the Mod
VHDL--traffic-light-reports-and-code
- 用VHDL实现交通灯项目，并用FPGA验证！-The traffic light project using VHDL and FPGA verification!