搜索资源列表
FPGABitcoinMiner
- 比特币的FPGA挖币机中SHA256的核心代码及测试用例，适合于自己开发比特币挖币机-vhdl based SHA256 computation code and testbench for bitcode miner. For developers that build their own mining machines
FIR-filter
- VHDL设计的FIR滤波器，由3个文件组成：FIR.VHD、PACK.VHD和signed.vhd。testfir.vhd为测试平台。-VHDL designed FIR filters, composed by the three documents: FIR.VHD, PACK.VHD and signed.vhd. The testfir.vhd is a testbench.
SDRAM_Modelsim
- 基于VHDL的SDRAM控制器源代码以及modesim验证工程的testbench-SDRAM controller based on VHDL source code and modesim verification testbench works
ethenete
- 基于verilog的三速以太网源程序，文件中包含源程序和测试程序。-tri_model ethernet source code based on vhdl languange, include source code and testbench in the file.
ALU
- 简易的VHDL程序，主要实现ALU的逻辑功能，进行选择和数据的移动。很适合初学者对VHDL的理解。内含有testbench可以进行Qutarus的仿真-Simple VHDL program, the main achievement of the ALU logic functions, to select and move data. VHDL is suitable for beginners to understand. Containing a simulation testbench
dac7564
- 基于VHDL的dac7564驱动程序和该程序的testbench测试程序-I DON T KOWN
yimaqi_beh
- 8位计数器作业中的behavioral描写，没有带testbench，已经通过-1. Construct VHDL models for 74-139 dual 2-to-4-line decoders using three descr iption types, i.e., behavioral, dataflow and structural descr iptions. Synthesize and simulate these models respectively in the en
hamming
- 32位海明码编码解码的vhdl代码，有testbench验证。-32 Hamming code encoding and decoding of vhdl code, testbench verification.
mcu8051
- 一个实现MCU51处理器的完整VHDL源代码，包含testbench-An implementation MCU51 processor complete VHDL source code, including testbench
ise_c8051
- r8051（c8051）IP源码，使用VHDL编写。整个工程通过ISE13.2实现，附带完整testbench，并实例化了rom和ram，可以运行c代码。工程内包含modelsim的仿真脚本，可以观测程序运行时的内部硬件工作情况。-r8051 (c8051) IP source code, the use of VHDL. The whole project is realized by ISE13.2, with complete testbench, and examples of the
simu01
- spartan 3 series ADC vhdl code testbench
SPI-Core_nguyen
- SPI Master Core HDL: VHDL 93 Compatibility: all FPGAs, CPLDs parameterization: - variable data width - Phase/polarity configurable - selectable buffer depth - serial clock devision due to system clock package usage: IEEE
1.2Register-VHDL-and-testbench
- 用d type flip flop 改成的n bit 的寄存器，分别用到了同步和异步2种方式-With d type flip flop into the n bit registers were used in the synchronous and asynchronous 2 ways
seq_detector
- 3比特的任意二值序列检测器(例如101、110、001等)。从任意序列中检测出三比特的序列。包含VHDL源码以及testbench测试源码程序。-The 3-bit binary sequence of any detector (e.g., 101,110,001, etc.). A three-bit sequence is detected from an arbitrary sequence. Includes VHDL source code and testbench test so
all-pole_filters_latest.tar
- All polar vector and its vhdl code with testbench
06168353
- The Fast Fourier Transform (FFT) is one of the rudimentary operations in field of digital signal and image processing. Some of the very vital applications of the fast fourier transform include Signal analysis, Sound filtering, Data compressio
Multiplier
- 我是2014级复旦的研究生。这是用VHDL语言设计的任意的M乘以N位的乘法器。设计中，被除数和乘数的位数是通过参数来设置的，可由你来修改。我已写好了testbench。可放心使用。-I am a 2014 graduate of Fudan University. This is an arbitrary M VHDL language designed by N-bit multiplier. Design, the dividend and the median multiplier is
TEXIO
- TEXIO study testbench passed VHDL FPGA CPLD simulation Altera quartus
testbench_top_level.vhd
- testbench for top level, vhdl, audio synthesizer, top level
CAVLE-h264
- 本压缩文件包含了h.264压缩算法中的CAVLE的编解码模块（Verilog和VHDL两个版本），包含有仿真的testbench测试文件，综合后可以直接使用-The compressed file contains the h.264 compression algorithm CAVLE codec module (Verilog and VHDL both versions), including a simulation testbench test file, can be used d