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DIVIDER
- 大家好，我是复旦大学的研究生。本资源是一个基于VHDL语言的M位除以N位的除法器。其中M/N ，商M位，余数是N位的。以Moim设计验证和验证。压缩包里有除法器的源文件和testbench。可加入工程，直接测试。鄙人测试都是无错误的。愿尊驾下载后，积极评价，以便于相互交流，学习。O(∩_∩)O谢谢.2015年5月7日于芬兰，图尔库。-Hello everyone, I am a graduate student at Fudan University. This resource is base
VHDL_Multiplier
- 三种 VHDL 实现乘法器的方法，可以用于学习FPGA的时序、组合电路，同时附带了 TestBench 程序-Three kinds of methods to achieve multiplier in VHDL, with TestBench
串并转换
- vhdl实现串并转换，其中附有源程序和testbench程序，可以用modelsim仿真
ddr2_controller
- A controller for DDR2 on FPGA with vhdl, content testbench, model and textfile-generation/data-detection using python.
debouncer_vhdl
- RTL and testbench implementations for a switch debouncer with support for multiple switches, written in VHDL.
trafficlight
- VHDL实现红绿灯，multisim测试通过，可直接烧录到FPGA板上进行测试,带testbench-VHDL realize traffic lights, multisim tested, can be burned directly to the FPGA board for testing, with testbench
SPI-master-P-tb
- SPI master VHDL realisation Also contains TestBench
M_UartRecv0_tb
- rs232串口基于VHDL的testbench代码 很有用的 经过验正的 -RS232 serial port based on testbench s VHDL code is very useful to the RS232 serial port based on testbench VHDL code is very useful to pass the test
uartlvds
- UART VHDL sources with FIFO-UART VHDL sources with FIFO,baudrate,receiver,transmitter,register,testbench
fpu_double
- The Verilog version of the code is in folder “fpu_double”, and the VHDL version is in folder “double_fpu”. There is a readme file in each folder, and a testbench file to simulate each core. These cores are designed to meet the IEEE 754 standard f
OpenMIPS_VHDL_study_v1.0
- 10天实现OPENMIPS处理器-VHDL版[内有详细代码，testbench和设计文档，十天教你学会MIPS架构CPU设计]-10 days to achieve the OPENMIPS processor-VHDL version [within a detailed code, testbench and design documents, ten days to teach you to learn MIPS architecture CPU design]
convolution
- 卷积 严格遵守时序的一维卷积运算，用testbench测试了-convolution write a VHDL file to compute one-dimensional convolution latency 14
VHDL-Code-and-TestBench-Code
- 实现了三个功能电路的程序：时钟分频电路；移位寄存器；序列检测器。-Including three parts:frequency divider shifting register sequential detector
simProcessorEx
- 一个简单微处理器内核的VHDL程序，包含源代码（位于Source目录内）及ModelSim仿真代码（位于testBench目录内）。使用该内核进行一个功能验证程序（位于simProc_test目录内）-a simple processor core program and test code based on VHDL language
boxingfashengqi
- 波形发生器的源代码，有正弦波，三角波，锯齿波，方波。modelsim仿真，包含testbench仿真代码，testbench用的verilog编写，波形发生器源代码用的VHDL编写。-Waveform generator source code, sine, triangle, sawtooth, square wave. modelsim simulation, testbench simulation code contains, verilog write testbench use, w
chuzuche
- 出租车vhdl程序，并带有testbench仿真程序，通过开始按键复位，然后根据行使信号进行公里计数，起步价3公里8元钱，超过3公里一公里1元钱-Taxi vhdl program, with a testbench simulation program, started by the reset button, then the exercise kilometer count signal, starting at 3 km 8 yuan, more than three kilometer