搜索资源列表
textio
- vhdl testbench的编写，textio的编写是一个难点，也是一个重点，而这是本人搜集的多篇关于textio的文章，同时附有简单注释!
vhdl实现alu的源代码
- VHDL实现ALU的源代码，并且提供了一个详细的testbench！-ALU VHDL source code, and provide a detailed testbench!
VHDL_Testbench
- VHDL中TestBench的编写，很详细，有例程
比较器的测试矢量
- 一个很好的testbench的例子。
sha-1.rar
- 本算法基于leon2协处理器接口标准，内含testbench，在modelsim中仿真通过，在ise9.2中综合及后仿真通过。,The algorithm is based on the leon2 co-processor interface standard, including testbench, ModelSim simulation in the adoption, in ise9.2 integrated and adopted after the simulation.
FPGA-PCI.rar
- 基于FPGA的PCI接口源代码及Testbench Verilog程序代码,fpag pci
sram
- sram操作vhdl源程序，内有sdram模型，控制器设计，及测试源程序-sram operating in vhdl \doc DDR SDRAM reference design documentation \model Contains the vhdl SDRAM model \route Contains the Quartus 2000.05 project files a routed controller design \simulation
TESTBENCH
- 一个关于testbech写法的文档，很经典-A written document on the testbech very classic
UART
- 用VHDL编写实现的UART控制器源码，自带testbench，解压后用ISE打开工程文件即可。-Prepared with the VHDL source code to achieve the UART controller, bring their own testbench, after decompression project file can be opened with the ISE.
testbench
- altera 最新的CYCLONE IV的pci-e核的testbench，VHDL源程序。-altera latest CYCLONE IV of the pci-e core testbench, VHDL source code.
Testbench(Verilog)
- verilog验证平台的使用 很不错 很详细 想具体-verilog verification platform is more like using a very good specific
Spartan3E-LCD
- 一个基于Spartan3E板子的LCD接受的代码附带testbench-A board of LCD-based Spartan3E accepted code with testbench
TestBench_Primer
- 是学习数字电路设计verilog语言，及Writing testbench的首先好书。-Writing testbench
testbench(vhdl)
- 是学习数字电路设计verilog语言，及Writing testbench的首先好书。-wrting testbench
writing-testbench
- 教你如何写VHDL或VerilogHDL的testbench文件，非常有利于FPGA的波形仿真-Teaches you how to write VHDL or VerilogHDL the testbench file, is very conducive to the waveform simulation of FPGA
Part-2-DWT-haar-using-VHDL
- Part 2 testbench for Discrete wavelet transfrom implementation in VHDL language Haar Filter
testbench
- VHDL和verilog的TESTBENCH 编写方法。非常好的资料。英文的,但很简单。-Written in VHDL-TESTBENCH. Very good information. In English, but very simple.
VHDL-counter
- The VHDL testbench Design, with source code and testbench in detail
VHDL-TESTBENCH
- 这是一篇用VHDL编写testbeach测试文件的详细讲解资料，举例讲解详细易懂，很实用-This is a VHDL explain in detail the information writing testbeach test file, for example, to explain in detail to understand, it is practical
VHDL——如何写简单的testbench
- 基于VHDL的testbench编写攻略(VHDL based on the preparation of testbench Raiders)