搜索资源列表
pll
- 用VHDL写的数字锁相环程序 pll.vhd为源文件 pllTB.vhd为testbench-pll.vhd : PLL written in VHDL hardware language. pllTB.vhd is a test program for pll.vhd.
SRAM.rar
- 瑞芯科技EFX400SL开发板上使用SRAM的工程源码,Rockchip EFX400SL the development of science and technology the use of SRAM on-board source of project
FinalCodelast
- last cordic for immplemantaion of cordic with vhdl language it has testbench
myself_uart_vhdl
- 自己写的，对串口的VHDL描述，有完整testbench，特别是详细的功能说明和注释。-Wrote it myself, on the serial port of the VHDL descr iption of a complete testbench, in particular, detailed functional descr iptions and notes.
Writing_Efficient_Testbenches
- vhdl语言 和verilog hdl语言的测试程序编写- testbench for vhdl and verilog
i2c.tar
- 是个I2C软核，使用verilog和vhdl实现的，含有testbench。-this is soft core of I2C in verilog rtl and VHDL.
bin2bcd
- Binary to BCD converter
shift
- Simple shift register with testbench in vhdl
divisor_n_bits_sin_restauracion
- vhdl divisor of n-bits without restaurecion metod. divisor de nbits en vhdl sin restauracion. con testbench.
EDA
- VHDL上机手册（基于Xilinx ISE） ___________________________________________________ 1 ISE 软件的运行 2 创建一个新工程 3 创建一个VHDL源文件框架 4 输入VHDL程序 *5 仿真 6 创建Testbench波形源文件 7 设置输入仿真波形 -eda
proc
- vhdl processor,5 commands,memory,testbench
venomgen
- venomgen - C source code of VHDL code generator for CRC, BCH and RS encoder -venomgen- C source code of VHDL code generator for CRC, BCH and RS encoder * polynomials can be entered via command line * variable bus width * automatic testbench
memoryarray
- 由VHDL撰写的两记忆体转置程序，内含testbench与转置源码。-VHDL written by the two memory migration procedures, includes testbench and migration source.
des
- des解密加密的verilog源代码其中包含有测试源代码，仿真结果图-verilog des decrypt encrypted source code which includes testing the source code, Simulation results
counter
- 计数器的VHDL源码及其对于的仿真Testbench 文件的编写-VHDL Code about counter for the "Simple Test Bench" example VHDL Code about adder for the "Simple Test Bench" example
arm9verilog
- AMBA AHB verilog Source code
elevator_controller
- vhdl elevator controller with testbench
code
- 一个基于fpga的简单的实时心电检测系统，包括与pc通讯和qrs检测两部分-A simple fpga-based real-time ECG detection system, including communication with the pc and qrs detection of two parts
uart2bus_latest.tar
- 文档详尽、已验证的UART工程，含有testbench文件。采用VHDL、Verilog语言编写。-Detailed documentation, has proven UART works with testbench file. Using VHDL, Verilog language.