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通信系统的仿真,Viterbi译码可用于卷积码等的译码解决方案,可以用于通信领域,本例子给出了基于matlab的程序,可用于实际的仿真!-communications system simulation, Viterbi decoder can be used as a convolutional code decoding solution, communications can be used, the example is given of the procedures based on
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该代码为Viterbi Decoder C/C++源程序。现为Doc文件。所含的vdsim.h在最后。-the Viterbi Decoder code for C / C source files. Doc is the document. Vdsim.h contained in the final.
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Viterbi Algorithm & Viterbi Decoder Matlab Code.(Provided both soft & hard decision ability). Note: The main function is viterbi.m
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verilog程序，实现了（2，1，4）卷积码编码，和基于回溯算法的维特比译码器-verilog program to achieve the (2,1,4) convolutional code encoding, and algorithm based on the back of the Viterbi decoder
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viterbi译码源代码,可以直接调用 The Viterbi decoder for convolutional codes-viterbi decoder source code, can be directly called The Viterbi decoder for convolutional codes
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用VHDL语言设计维特比 解码器 是VHDL原代码用ModelSim XE III 6.3c软件实现仿真-Language Design with VHDL Viterbi decoder is the VHDL source code with ModelSim XE III 6.3c software simulation
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Viterbi decoder source code
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Viterbi译码器的FPGA实现代码,来在国外大学论坛.-Viterbi decoder implementation of the FPGA code to the Forum at foreign universities.
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FPGA-based Viterbi convolutional coding and decoding of the Research and Implementation-Convolutional code encoder and Viterbi decoder design
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Viterbi decoder for nonsystematic convolutional code. The encoder could be designed arbitrary through the generate matrix and parameter k. The number of row of generate matrix is output bits, and collom is constraint length. Parameter k is the number
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matlab code for viterbi decoder
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Its a hard decision viterbi decoder that i built for my final year project.it decodes the convolutionally encoded data of code rate 1/2 having constraint length of 3.
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viterbi译码器的Verilog实现,(3,1,7)零尾卷积码-viterbi decoder implementation by verilog HDL （3，1，7）zero tail conventional code
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卷积码维特比译码器设计输出完整电路进行误码率分析-Convolutional code Viterbi decoder integrated circuit design of the output bit error rate analysis
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paper format that includes Viterbi Decoder complete VHDL code for the document. Nh format paper format that include s Viterbi Decoder complete VHDL code for the document. Nh format paper format that includes Viterbi Decoder complete VHDL code for the
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vhdl code for viterbi decoder
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verilog code for viterbi encoder and decoder
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编码方式为213的Viterbi卷积码编码器和译码器的FPGA的实现，包含整个QuartusＩＩ的工程文件，解码方式为寄存器交换法-Encoding for the 213 convolutional code encoder and Viterbi decoder FPGA realization of the project file that contains the entire QuartusII, decoding method for the register exchange
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this codes are for convolution encoder and Viterbi decoder synthesis and implementation.
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