搜索资源列表
buxian
- 布线算法是VLSI中重要的算法。buxian.cpp基于模拟退火实现的布线算法。-VLSI routing algorithm is an important algorithm. buxian.cpp routing algorithm based on simulated annealing implementation.
upload1
- fault tolerant vlsi design journal papers
VLSI_Notes
- labs manual and notes of vlsi
vlfft
- 基于TMS320C66x系列DSP的超大规模FFT实现，可作为《TMS320C66x KeyStone架构 多核DSP入门与实例精解》书中5.3小节的例程使用。-Based on VLSI FFT TMS320C66x series DSP implementation, as a routine use TMS320C66x KeyStone architecture and multi-core DSP Starter instance fine solution, the book s
vlsi-design2
- 一位8421BCD编码的十进制数加减法器，电路具有进位、借位功能-A 8421BCD encoding decimal adder subtracter circuit has the function, carry out.
vlsi-design3
- 电路具有四路4_bit字宽的串行输入总线，四路4_bit字宽的输出总线信号的电路。 电路完成将串行输入信号A[3..0]、B[3..0]、C[3..0]、D[3..0]（大小排列无序）以数值大小排序输出的功能，输出X3[3..0]、X2[3..0]、X1[3..0]、X0[3..0]中X3最大，X0最小。输入数据是无符号整数。 -Circuit with four 4_bit word wide serial input bus, four 4_bit word wide output
Area-Delay-Power-Efficient-Carry-Select-Adder-usi
- Implementation of IEEE 2015 paper for Area–Delay–Power Efficient Carry-Select Adder using VLSI verilog .The code tested by modelsim and also main program is test.v . If have any trouble mail to anandg.embedd@gmail.com-Implementation of IEEE 2015 pape
1
- DNA Cryptography and Trellis Algorithm
VLSI Architecture for Real-Time HD1080p
- 3d-hevc虚拟视点合成算法；硬件实现.VSRS算法(3d-hevc virtual view synthesis algorithm; hardware implementation;.VSRS algorithm)
bist 2017 paper
- A new low-power (LP) scan-based built-in selftest (BIST) technique is proposed based on weighted pseudorandom test pattern generation and reseeding. A new LP scan architecture is proposed, which supports both pseudorandom testing and deterministi
Microwind
- A good images made by microwind for VLSI
智能优化算法
- 优化技术是一种以数学为基础，用于求解各种工程问题优化解的应用技术。作为一个重要的科学分支，它一直受到人们的广泛重视，并在诸多工程领域得到迅速推广和应用，如系统控制、人工智能、模式识别、生产调度、VLSI技术和计算机工程等。鉴于实际工程问题的复杂性、约束性、非线性、多极小、建模困难等特点，寻求一种适合于大规模并行且具有智能特征的算法已成为有关学科的一个主要研究目标和引人注目的研究方向。 20世纪80年代以来，一些新颖的优化算法，如人工神经网络、混沌、遗传算法、进化。(Optimization te
Coding Files
- Through this paper our attempt is to give a onetime networking solution by the means of merging the VLSI field with the networking field as now a days the router is the key player in networking domain so the focus remains on that itself to get a good
VLSI_IEEE_2016_List
- VHDL IEEE 2016,2017 Project List
ALUYEDEK
- alu circuit design for vlsi and 4 bits alu
IDE
- thesis related to vlsi area, pll and frequency synthesizer div()
3. Comparator
- EXCLUSIVE OR and EXCLUSIVE NOR gates may be viewed as 1-bit comparators. Figure 1(a) shows an interpretation of the 74x86 XOR gate as a 1-bit comparator
Chopper_IA
- A small-area low-ripple chopper instrumentation amplifier (IA) using a sample-and-hold circuit
CMOS Nested-Chopper
- A CMOS nested-chopper instrumentation amplifier is presented with a typical offset of 100 nV.
CMOS_IA
- A low-noise CMOS instrumentation amplifier intended for low-frequency thermoelectric microsensor applications