搜索资源列表
ml310_base_linux_kernel_config
- xilinx FPGA,可用于xupv2p开发板的嵌入式Linux内核配置文件-Linux xupv2p
arithmetic
- 这是xilinx的FPGA实现各种算数运算的全部基于MATLAB的模型文件,包括加减乘除等-This is the xilinx arithmetic FPGA to achieve the full range of MATLAB-based model of documents, including multiplication and division, such as addition and subtraction
BGA1
- 本应用指南针对 FT256 1 mm BGA 封装的 Spartan™ -3E FPGA,讨论了低成本、四至六层、 大批量印刷电路板 (PCB) 的布局问题,同时探讨高速信号和信号完整性 (SI) 因素对低层数 PCB 布局的影响。-Application Guide for the FT256 1 mm BGA package, Spartan ™-3E FPGA, the discussion of the low-cost, four to six, high-
tftpserver
- TFTP server for Microblaze Xilinx
Xilinx_constraints.pdf
- detail timing constraint for Xilinx FPGA design
module
- 基于VHDL语言,设计7段LED液晶显示屏,可以下载到相关的xilinx开发板上进行验证-Based on the VHDL language, design 7 LED LCD screen, can be downloaded to the relevant board to verify the development of xilinx
Exp1-Led
- 本次实验使用 Xilinx FPGA的开发工具 ISE6.x,新建一个工程,并进行综合、布局布线、 下载配置。 这里建立的工程是使用 Create-SOPCMB上的发光二极管显示一个八位二进制计数器, 发光二极管亮表示该位为 0。 -Experimental use of the Xilinx FPGA development tools ISE6.x, create a new project, and comprehensive, the layout of wiring, d
RAM
- 用VHDL编写一个字长16位,容量128B的RAM控制实现程序,并进行设计综合和功能模拟 。含源程序,及实验要求。适合初学者学习使用。-VHDL prepared with a 16-bit word length, 128B of the RAM capacity to achieve process control and design of analog integrated and functional. Containing source code, and experimental
HDB3_coder
- 实现了将64K低速NRZ码复接成2.048M高速HDB3码及其解复接过程,同时还用同步状态机剔除假同步和假失步的状态 -Achieved the 64K low-speed NRZ code 2.048M into high-speed multiplexing and demultiplexing HDB3 code then the process also removed using false synchronous state machine synchronization and f
XILINX
- not so good BPSK software matlab
SysgenQAM16Demodulation
- 采用Xilinx的Sysgen工具建立的16QAM调制解调模型,其中包括信源生成、多普勒频偏、载波跟踪环路等。-Established by the use of Simulink model of 16QAM modulation and demodulation, including source generation, Doppler shift, such as carrier tracking loop.
add4bit
- 一位全加器的VHDL源码与TEST BENCH.XILINX下通过-A full adder and the VHDL source code through TEST BENCH.XILINX
src
- DQPSK modulation with XILINX FPGA. 2 level butterworth analog filter for I & Q D/A output. -DQPSK modulation with XILINX FPGA. 2 level butterworth analog filter for I & Q D/A output.
stopwatch
- The program is written in verilog to accomplish functions of a stopwatch. It can be implemented in Xilinx FPGA spartan 3 board.
xapp460
- xilinx hdmi tx rx verilog code
xapp856
- 基于FPGA的SFI接口实现(VHDL,Verilog and doc)-SFI-4.1 16-Channel SDR Interface with Bus Alignment
ddr_usb
- 将256位数据宽度 通过两级FIFO 转成16位 使用XILINX的ISE10.1完成设计 此为工程文件 有仿真结果-The 256-bit data width conversion FIFO through the two 16-bit using the XILINX s ISE10.1 to complete the design documents for the works in this simulation results
dds_easy
- 直接频率合成DDS模块的ise工程,可以直接下载,在Spartan3/Spartan3E上验证通过。该DDS模块可以产生双通道的不同频率的正弦波,也可以产生同频的任意相位差的相移波形。本模块累加器位数为32位,可以产生12位相位精度12位量化精度的正弦波。该设计例化一个Block Ram,为节省储存空间仅需要储存1/4周期的数据。根据需要,可以重新修改数据,改变波形。-DDS direct frequency synthesizer module ,ise project, can be dir
KEY
- EDK 中的外部中断 键盘中断 在火龙刀上实现-The external interrupt EDK