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100vhdl0621
- VHDL应用程序100例，适合初学者研究及练习 其中包含加法器译码器等多程序。-100 samples of VHDL, it is fit for beginner to study and practice. Adding machine, decoder and others are included.
1_ADDER
- 这个是带输入的加法器vhdl代码,是带有输入端和进位的.-with imported Adder VHDL code, which is input into and spaces.
89_full_adder
- 这个是带先行进位的加法器的vhdl代码,比较复杂,仅仅供大家参考.-into first place with the addition of VHDL code more complicated, just for reference.
dsdad
- 关于bcd码加法器 第一个是一位的 通过了 第二个是四位的没通过?赜赽cd码加法器 第一个是一位的 通过了 第二个是四位的没通过-on bcd yards Adder is a section through one of the second of four is not the adoption of codes increases bcd instruments used in a section of the passage of a second four is not the ado
小学生加法器设计
- java小应用程序开发，小学生加法器实现，包含友好界面，过程简洁，算法详细。-small application development, students achieve Adder, including friendly interface, simple process, the algorithm in detail.
44
- 加法器测试平台，具有键盘输入，屏幕显示功能-Adder test platform with a keyboard input, screen display
mul
- 加法器树乘法器结合了移位相加乘法器和查找表乘法器的优点。它使用的加法器数目等于操作数位数减 1 ，加法器精度为操作数位数的2倍，需要的与门数等于操作数的平方。 因此 8 位乘法器需要7个15位加法器和64个与门-Adder tree multiplier multiplier combination of shift and add multiplier advantage of look-up table. It uses the adder operand is equivalent to
testZ
- 八位加法器的原理图实现方法和一位半加器 全加器的原理图实现-Eight adder schematic diagram of the method and a half adder full adder schematic diagram of the realization of
adder
- 本设计是做了一个32位超前进位加法器，能够快速计算-This design is made of a 32-bit lookahead adder, to quickly calculate
FPGAVerilogHDLcode.RAR
- 一些例程供参考，包括加法器，减法器，多路选择器-failed to translate
cnt_10
- 十以内的加法器，实现十以内的加法功能，最高位清零(en less than adder, to achieve the addition function within ten, the highest clear)
基于FPGA的四位加法器
- 基于FPGA的四位加法器verilog语言代码(be basaed upon FPGA adder4)
六进制
- 非常基础且实用的六进制加法器，采用VERILOG语言编写而成。(very common and uesfully tool--counter6, iy is writed by Verilog.)
add
- 八位加法器的说明和算法，以及程序说明过程和算法过程(The descr iption and algorithm of the eight adder and the process of program descr iption and algorithm)
add
- 使用verliog语言去FPGA实现10位加法器(Using FPGA to implement 10 bit adder)
同相端加法器和倒向端加法器
- 该资料为同相端加法器和倒向端加法器的mathcad计算文档(The data is Mathcad computing document of the same phase terminal adder and the backward end adder.)
jfq
- 本程序利用vs2013与MFC编写简易的加法器，可以进行加法计算。(This program uses vs2013 and MFC to write simple adders, which can be added to calculate.)
基于FPGA的单精度浮点数乘法器设计
- 《基于FPGA的单精度浮点数乘法器设计》详细介绍了按照IEEE754标准在FPGA上实现单精度浮点加减乘除的方法(The design of single precision floating point multiplier based on FPGA introduces in detail the way of realizing single precision floating point addition, subtraction and multiplication and div
si四位加法器
- 内含三个普通的四位加法器，adder，adder4-2，adder4-3(library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity full_adder is port( a,b,ci :in std_logic; s,co :out std_logic); end entity; architecture rtl of full_adder is begin s&
流水线乘法累加器设计
- 调用寄存器LPM,流水线加法器LPM,流水线乘法器LPM等模块实现一个8位流水线乘法累加器。(Call a register LPM, pipelined adder LPM, pipeline multiplier LPM and other modules to achieve a 8 bit pipelined multiplication accumulator.)