搜索资源列表
FIFO
- 基于FPGA的FIFO控制器的设计与实现,ISE,verilog-FPGA-based design and implementation of FIFO controller, ISE, verilog
FIFO
- verilog编写的读写fifo的源码,包括sram的读写控制-verilog source code written to read and write fifo, including the sram to read and write control
sdh
- SDH是现代光纤通信中广泛应用的数据传输格式,在SDH帧结构中,前9列为开销字节,它包含了很多重要的信息,本程序为SDH开销的接收处理,查找帧头,分频,勤务话字节E1异步fifo。可拆为三段源代码,不知道能不能抵三个程序-SDH is a modern optical fiber communication is widely used in data transmission format, in the SDH frame structure, as the former 9 overhea
fifo
- fifo 即实现数据的先进先出,是用verilog编写的 就撒开了几分-fifo hjahfjhsjeikkdnakfnakjfakjkf
VFIFOzipe
- 用verilog实现异步FIFO,代码中有两个模块,使用时时注意顶层模块和底层模块,用quartus2即可打开直接使用。 -Asynchronous FIFO, with verilog code has two modules, using the constant attention of top-level module and bottom module with quartus2 to open.
aasyn_fiffos
- verilog编写的异步fifo源代码,asyn_fiifo.v为顶层,调用其他四个文件, -verilog prepared the the asynchronous fifo source code, asyn_fiifo.v for the top floor, calling the other four documents,
fifo
- 同步fifo的verilog代码,很好的资料,值得学习-Synchronous fifo verilog code, very good information, it is worth learning
fifo
- 异步fifo ,verilog 源代码,含工程文件,modosim 下运行-Asynchronous fifo verilog source code containing the project file run modosim
exercise3
- 用verilog实现dsp与Fpga接口的同步设计,其功能包括读写操作及四个功能模块,采用两个fifo实现不同时钟域的地址与数据的转换,在quartus ii11.0环境下运行,运行此程序之前需运行将调用fifo。-Dsp using verilog achieve synchronization with Fpga interface design, its features include read and write operations and four functional modul
fifo
- 异步FIFO实现 verilog代码,利用格雷码消除亚稳态-Asynchronous FIFO realize verilog code, Gray code to eliminate the use of metastable
fifo_verilog
- 16位FIFO的硬件电路,使用verilog实现。文件内含组合逻辑和寄存逻辑两种方法的实现,以及对应的testbench测试代码-16 FIFO hardware circuits using verilog implementation. File contains a combination of logic and storage logic to achieve the two methods, and the corresponding testbench test code
FIFO(verilog)
- FIFO 的verilog代码,包含测试源码,可以参考学习FIFO的编写-FIFO written with verilog
async_fifo
- 异步FIFO verilog 代码 复位到空,读侧以及写侧复位均可以使两侧同时复位,且基本同时放开。-ayschronized FIFO verilog code
oscillo_1
- 简单数字示波器的verilog设计,涉及到时钟同步,FIFO的配置和使用,非常适合用来学习FPGA以及熟悉quartus II 软件。(digital oscilloscope design)