搜索资源列表
dff-n-d-latch
- Dlatch and D Flipflp code with testbench in Verilog
cordic_1-0
- 关于cordic算法的C MODEL实现，包括几种不同的模式，如求模值、求相角，求COS,SIN函数等。程序还包括TESTBENCH测试程序。-About cordic algorithm C MODEL implementation, including several different modes, such as modulus values, seeking phase angle, seeking COS, SIN function and so on. TESTBENCH test
adder
- 包含32位有无符号数的加减法，verilog语言描述，加法器分别采用行为级描述、行波进位、平方根进位三种描述方法，并有简单的testbench-32bits adder with addition and subtraction function. verilog HDL language . three kinds of implementations: adder behavioral descr iption, ripple carry, the square root of the ca
lab1
- apb transactions with DUT, testbench including interface test cases , top
Arbitrary-_odd_-frequency_VHDL_code
- 任意奇数分频的VHDL代码和testbench测试VHDL代码，经过ISE的ISim仿真工具测试，模块功能准确有效，特此分享！-Arbitrary odd frequency of VHDL code and test VHDL testbench code, after the ISE ISim simulation tool to test module functions accurately and effectively, would like to share!
fifo_verilog
- 16位FIFO的硬件电路，使用verilog实现。文件内含组合逻辑和寄存逻辑两种方法的实现，以及对应的testbench测试代码-16 FIFO hardware circuits using verilog implementation. File contains a combination of logic and storage logic to achieve the two methods, and the corresponding testbench test code
Haffman-encoding
- verilog implementation of huffman encoder with testbench
Multiplier
- 我是2014级复旦的研究生。这是用VHDL语言设计的任意的M乘以N位的乘法器。设计中，被除数和乘数的位数是通过参数来设置的，可由你来修改。我已写好了testbench。可放心使用。-I am a 2014 graduate of Fudan University. This is an arbitrary M VHDL language designed by N-bit multiplier. Design, the dividend and the median multiplier is
Example-b8-1
- 使用ModelSim对Altera设计进行功能仿真的简要操作步骤 1.建立仿真工程 2.Altera仿真库的编译与映射 3.编译HDL源代码和Testbench 4.启动仿真器并加载设计顶层 5.打开观测窗口，添加信号 6.执行仿真-Using ModelSim Altera design for functional simulation brief Procedure 1. Create a simulation project Compilation and map
Example-b8-2
- 使用ModelSim对Altera设计进行时序仿真的简要操作步骤 1.建立工程，设置仿真工具选项参数 2.使用Quartus II编译工程 3.建立仿真工程 4.Altera仿真库的编译与映射 5.编译HDL源代码和Testbench 6.启动仿真器并加载设计顶层 7.打开观测窗口，添加信号 8.执行仿真-Using ModelSim Altera design for timing simulation of brief steps 1. Establish pro
MyFFT
- 该程序可实现基于IP核的FFT算法，TESTBENCH用TEXTIO输入输出数据-The program can achieve FFT algorithm based on IP core, TESTBENCH based on TEXTIO input and output data
pud_ben
- Verilog HDL source code of generating a ROM file (in Quartuss) and testbench in Modelsim (verification)
sv_lab_switch
- system verilog ASIC 验证平台编写详细实例-system verilog testbench for ASIC
串并转换
- vhdl实现串并转换，其中附有源程序和testbench程序，可以用modelsim仿真
ImageProcessor-(1)
- a testbench which can be used to use in imge processing. this creates pixel values depending on the threshold given. Can be used to sharpen images using FPGA
Counter3
- 基于Xilinx 的ISE 14.7 的计数器程序，包含testbench文件和约束文件-Based on the Xilinx ISE 14.7 Counter program, including testbench and constraints files
filter_tb
- 滤波器的testbench，测试模块，自带输入输出-Filter testbench, test module, comes with input and output
gen_tb
- 自己写的perl程序，可以根据逻辑代码的top文件自动生成verilog的testbench，方便做simulation，提高效率-perl program,written by myself, can automatically generate verilog testbench according to the logic of the code top file, easy to do simulation, improve efficiency
class09_A
- Verilog 状态机编写按键消抖，并且testbench-Verilog write key debounce
testbench.sv
- RS 编码和解码Verilog Code, 实现了RS（544,514)的编码和译码；--RS Coding and Decoding Verilog code， implement RS（544,514)