搜索资源列表
testbench
- ddr sdram controller datd module source code
Memory
- Example of a FIFO code in verilog language, to control a bus. With a memory stack and a testbench.
alu
- ALU modeling verilog codes and testbench
cpu86model
- This is intel 8088 x86 IP core, contain software complier & modelsim testbench
TESTBENCH
- 一个关于testbech写法的文档，很经典-A written document on the testbech very classic
mem-ctrl-rtl
- 实现对ddr的控制，可以在fpga的仿真环境下跑程序，并有testbench可以参考-implement ddr control
wave
- TESTBENCH OF CARDIO SYS-TESTBENCH
venomgen
- venomgen - C source code of VHDL code generator for CRC, BCH and RS encoder -venomgen- C source code of VHDL code generator for CRC, BCH and RS encoder * polynomials can be entered via command line * variable bus width * automatic testbench
multiplier8x8
- 8位定点乘法器，支持有符号数/无符号数运算。采用4-2压缩树结构，并提供testbench。-It is an 8-bit fixed-point multiplier, supporting signed/unsigned operations. Wallance tree structure with 4-2 compression. Provides testbench.
adder_4
- 详细介绍了四位加法器的verilog代码，还包括详细的testbench代码。-Details of the four adder verilog code, also includes detailed testbench code.
booth_mul
- booth乘法器，通过booth编码相乘，包括了testbench-booth multiplier, multiplied by booth encoding, including the testbench
vhld_tb_latest.tar
- 一个VHDL的测试平台，可以用来验证MircroProcessor，有完备的文档和代码。-A testbench based on VHDL language, you can apply it to verify a simple mircroprocessor, include complete ducoment and sources
inout_test
- verilog inout端口的测试程序 帮助理解Verilog语言inout端口的使用（包括Verilog程序和testbench）-verilog inout port test program to help understand the use of the Verilog language inout port
VMMing-a-SV
- vmm不错的学习资料，如何搭建testbench，很多实用的例子。推荐初学者。-study vmm of system-verilog
Full-Adder
- 用VHDL实现的全加器，采用dataflow style编写，是学习VHDL入门级的好范例. 包括主程序和测试程序-Full adder by using VHDL, dataflow style writing. It is a good example of VHDL especially for the entry-level leaner（Testbench included）
mux_4_to_1
- 基于verilog的四选一的设计，附带testbench，并且测试通过-Based on the four design in verilog, incidental testbench, and the test passes
pcm
- verilog 的代码，是pcm采编器，经过验证的，可以用，并且附带上testbench文件。-The verilog code pcm editorial, proven, you can use, and comes on the testbench file.
CRC-5
- 用于RFID的CRC5模块，和相应的testbench，已在quartus和modelsim中进行功能验证-For RFID CRC5 module and the corresponding testbench, functional verification in Quartus and modelsim
filter
- verilog implementation of structural FIR filter. Contains testbench, including sample data and coefficients.
shift-register-and-testbench
- Shift register and testbench in verilog