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statemachine11.2
- 推荐下载,verilog状态机实例.体现了流水线思想的应用 -recommend downloading Verilog state machine example. Pipeline reflects the thinking of the application
8.10
- 强烈推荐下载,verilog状态机实例.可以在modelsim下运行. -strongly recommend downloading Verilog state machine example. In modelsim running.
jiaotongdeng
- 这程序是利用状态机来控制交通灯verilog码-This procedure is the use of state machine to control the traffic lights verilog code
c73a2ceb-09a5-4366-83ea-78b08c6200eb
- jtag TAP控制状态机代码 verilog VHDL-jtag TAP state machine code
statemachine
- 用verilog HDL实现状态机的设计-Verilog HDL make the state machine come true
IOcontrol
- 输入输出控制的状态机,verilog HDL源码-Input and output control state machine, verilog HDL source
Verilog
- 交通灯状态机设计的完整Verilog代码-Verilog
conv_vhdl
- 用Verilog实现卷积码(2,1,2)的编码器,采用状态机来完成在modelsim下的仿真-Verilog implementation using convolution code (2,1,2) encoder, using a state machine to complete the modelsim simulation under the
serial_in
- verilog 串并转换程序 状态机 有4位前导码 共转换3位 可自己修改后转换更多的串行数据位-Verilog serial signal to parallel signal transfer
ttraafficLighr
- <p>交通灯状态机的实现,用verilog HDL编程与开发,Xillinx ISE 6仿真,在实际电路中的到验证. 已通过测试。</p> -<p> The implementation of the traffic light state machine, using verilog HDL programming and development, Xillinx ISE 6 simulation, to verify the actual circui
state-machine-program
- Verilog三段式状态机.pdf Verilog时序电路及状态机设计.ppt Verilog有限状态机设计.ppt 状态机.ppt 用状态机原理进行软件设计.pdf 有限状态机.pdf 有限状态机.ppt 状态机原理及用法.pdf 对状态机初学者有帮助。 -Verilog three-state machine the pdf Verilog Sequential Circuits and the state machine design. Ppt Veri
v16bbit_boothe
- verilog程序源码,实现两个16bit数乘法,使用booth算法,一种基于状态机实现,分层层次为datapath与controller两个子模块,testBench测试通过 -verilog program source code, and two 16bit multiplication using booth algorithm, based on the state machine implementation, the hierarchical level for the da
paomadeng2
- 简单的跑马灯verilog程序,笔者是初学者,利用简单状态机编写的-Simple Marquee verilog program, the author is a beginner, use a simple state machine to write
AD9854verilog
- verilog 编写的AD9854配置代码 通过状态机转换来配置AD9854-CONGIURE the ad9854 dds
fVerrilog_Devr
- 朋友,我是Jawen.看到先前上载的一套CPLD开发板的VHDL源码挺受欢迎的,现在就将她的Verilog源码也一并贡献给大家:8位优先编码器,乘法器,多路选择器,二进制转BBCD码,加法器,减法器,简简单易懂状态机,四位比较器,7段数码管,i2c总线,lcd液晶LCD显示出来,拨码开关,串口,蜂鸣器,矩阵键盘,跑马灯,交通灯,数字时钟 可直接使用。 -Friends, I Jawen. See previous upload a CPLD Development Board VHDL so
verilog
- 一些基本的Verilog 代码 包括基本的分频器设计,交通灯设计,自动售货机设计,有限状态机的设计-Some basic Verilog For freshman
class09_A
- Verilog 状态机编写按键消抖,并且testbench-Verilog write key debounce
class8_FSM
- 序列检测机(状态机实验),是Verilog状态机最基本的小实验,用于体会状态机的原理和作用(原作者:小梅哥)(Sequence detection machine is the most basic small experiment of Verilog state machine)
fsm3
- verilog状态机实验,说明一个状态机的生成过程(Verilog state machine experiment, which illustrates the generation process of a state machine)
new.v
- 状态机写的axi slave,模式较少,基本功能齐全,轻便,仿真综合通过(AXI4 slave programmed by state machine approach)