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picieee.tar
- The Synthetic PIC is a synthesizable VHDL descr iption of the basic Microchip PIC 16C5X microcontroller. It is written in the ViewLogic VHDL environment (Workview PLUS 5.2). It has successfully been synthesized to the XC4000 family, although
SinusGen1
- sine wave vhdl code that generates sine wave output using logibox in xilinx
henon
- chaotic generator of henon by xilinx sysgen and simulink
fpga_memory_rev_1_0
- Various memories for Xilinx and Altera FPGA devices. Single-port and Dual-port versions with various numbers of read and write ports. Bundle also includes read-first and write-first varieties with sync and async clocks. All memory compo
jj
- 本题设计一个数字存储示波器，以Xilinx公司20万门FPGA芯片为核心，辅以必要的外围电路（包括信号调理、采样保持、内部触发、A/D转换、D/A转换和I/O模块），利用VHDL语言编程，实现了任意波形的单次触发、连续触发和存储回放功能，并按要求进行了垂直灵敏度和扫描速度的挡位设置。信号采集时，将外部输入信号经信号调理模块调节到A/D电路输入范围，经A/D转换后送入FPGA内部的双口RAM进行高速缓存，并将结果通过D/A转换送给通用示波器进行显示，完成了对中、低频信号的实时采样和高频信号的等效采
couter
- 这是一个基于Xilinx Spartan3e开发板的非常简单的一个源代码，对于初学者可以用来熟悉Fpga的开发流程用。-This is a very simple code based on xinlinx Spartan3e board,it s very useful for beginner to study FPGA.
bpsk_dsp
- xilinx的一些例程，初学者可以看看相关的文件，以作深入学习-xilinx some routines, beginners can take a look at the documents related to in-depth learning
FIR
- 这是一个在MATLAB上编写的FIR滤波器程序，并能被AccelDSP综合，下载到Xilinx上进行硬件仿真，适合对AccleDSP学习的人应用-This is a MATLAB program to write the FIR filter, and can be integrated AccelDSP downloaded to the Xilinx on hardware simulation, suitable for application on AccleDSP learn,
IIR
- 一个MTLAB编写的IIR滤波器，可以通过Xilinx AceelDSP 综合生成硬件模块下载到开发板仿真的例子-Prepared a MTLAB IIR filter can be generated through the Xilinx AceelDSP integrated hardware modules downloaded to the development board simulation example
xilinx_microblaze_EDK
- Xilinx官方的6个EDK实验(中文版)-xilinx_microblaze_EDK_example_trainning
xilinxchipscopeprov8.1ikeygenz.w.t
- xilinx chipscope 8.1
xilinxisev6.1ikeygenror
- xilinx ise 6.1 keygen
Virtex_Analog_to_Digital_Converter
- adc转换程序，在Xilinx的FPGA上实现-adc conversion program, implemented on the Xilinx FPGA
dbox2-ide
- Die Dateien sind die Sourcen um die Firmware des IDE-CPLD zu generieren. Project-Files für die Xilinx-Software habe ich nicht gespeichert, da diese leicht neu generiert werden kö nnen. Zuletzt habe ich die Version ISE 8.2 verwendet
lupa4000_testSDMA
- Lupa test in DMA. Source for platform Xilinx/
Lab4-new
- Embedded system debuggin xilinx
edk_user_repository.tar
- xilinx network driver
generate-bit-and-mcs-files
- 描述了xilinx的ise工具，如何生成bit文件和mcs文件，一步步都含有截图，绝对原创-Describes the ise xilinx tools, how to generate the bit file and mcs file, step by step with screenshots are absolutely original
awgn
- AWGN Xilinx Logicore