搜索资源列表
fft_test3
- matlab simulinc file for calculating xilinx fft core using system generator
fft_compare
- matlab file to compare the results of fft function of matlab with fft of xilinx core generator
irig_b
- 用来实现IRIG_B码的解码程序，在XILINX ISE上运行过没有问题，-Used to achieve IRIG_B code decoding process, in XILINX ISE run-off is no problem,
example_design
- xilinx pcie总线 pio模式下的控制器代码。包含接收发送模块，存储模块，控制模块等。
DAC3283
- Xilinx数模转换芯片DAC3283说明文档。-Xilinx chip DAC3283 digital-analog converter documentation.
src
- SRC IMPLIMENTATION ON VHDL USING XILINX AND FPGA GIVES HIGH SECURITY IN DATA TRANSMISSION
xilinx_ise
- Xilinx ISE 14.4 Lincense，实测可用-Xilinx ISE 14.4 Lincense, actual available
FIFO
- 这是一个在xilinx下运行的关于FIFO的IP核设计的程序。-This is a run on the FIFO xilinx IP core design process.
Rashed
- simple Adder in verilog (xilinx)
yimaqi_beh
- 8位计数器作业中的behavioral描写，没有带testbench，已经通过-1. Construct VHDL models for 74-139 dual 2-to-4-line decoders using three descr iption types, i.e., behavioral, dataflow and structural descr iptions. Synthesize and simulate these models respectively in the en
I2C_Slave
- I2C从机的Verilog实现与仿真。使用XILINX软件完成。-I2C from Verilog and simulation machine implementations. Use XILINX software.
ExamTechAss2009
- un controller pi par le langage VHDL xilinx ise design 13.2
deinterlace
- Xilinx提供的一种利用线缓存进行插值的隔行变逐行程序，比普通算法效果有很大改进。-Xilinx offers a way to use line cache interpolation of interlaced programs line by line, than the general algorithm effect is a great improvement.
Greedy_snake
- 利用Xilinx ISE平台在FPGA实验板和VGA显示屏上完成简单的贪吃蛇游戏-Use Xilinx ISE platform to complete a simple Snake game on FPGA experimental board and VGA display
Piano
- 用VHDL写的，实现触摸屏电子琴的功能，可录音、放音，适用于赛灵思的板子。-Written using VHDL realize the function of touch-screen keyboard, recordable, playback for Xilinx board.
pacman_vhdl_xilinx
- VHDL version of Pacman. Intended to run under Spartan II over the Xess dev.board but easily portable to any other Xilinx platform. Contains full project with all bitmaps and sounds.
powerlink
- powerlink 次站VHDL源码，可以实现4中不同的模式，基于xilinx平台。-powerlink slave VHDL sourcecode，which is based on Xilinx platform.
Washing_VHDL-v1
- 一个全自动洗衣机，三个状态及显示。 开发环境为xilinx ise-a autowasher with 3 states
ml506_bsb_std_ip
- this files ml506 source for xilinx
vivado2014.1-license
- xilinx最新软件Vivado2014.1版本的license，安福利FAE提供，绝对好使。-Vivado2014.1 xilinx latest software version license, Avnet FAE offer absolutely so.