搜索资源列表
100vhdl0621
- VHDL应用程序100例，适合初学者研究及练习 其中包含加法器译码器等多程序。-100 samples of VHDL, it is fit for beginner to study and practice. Adding machine, decoder and others are included.
ISE_chinese
- 通俗的介绍了ise的使用方法，对vhdl和verilog开发的初学者来说是不错的选择-popular introduction to the use of the method ideally, the VHDL and Verilog development of the newcomer is a good choice
enc
- HDB3编码器 使用VHDL编制 对于基带传输很有用的程序-HDB3 encoder using VHDL preparation for baseband transmission useful procedure
EDA138_457
- 用VHDL语言来实现一个电子时钟，可以调时间。小时，分，秒。可以下载到实验箱来运行验证。适用与大多数实验箱-use VHDL to achieve an electronic clock, the time can be set aside. Hours, minutes and seconds. Experiments can be downloaded to the box to run test. Apply with the majority of experimental boxes
autosale
- VHDL编写的自动售货机，带找零、退币功能，数字电路课程设计！内附常态图，和dofile波形模拟文件-VHDL prepared by the vending machines, have sought to bring, the coin features, digital circuit design courses! Enclosing normal map and document dofile waveform simulation
trafficlight
- VHDL编写的交通灯程序，有倒计时功能，数字电路课程设计，内附状态图和dofile波形模拟！-VHDL prepared by the traffic lights procedures, the countdown function, digital circuit design courses, enclosing a state map and dofile waveform simulation!
cdu16
- 一个简单的不得了的........VHDL程序... 行了吧-a simple incredible ........ procedures ... threw VHDL
S3BOARD-demo
- vga 程序 demo程序，可以用，线条显示 可编程逻辑设计vhdl语言编写-vga procedures demo procedures can be used, the lines show programmable logic design, VHDL language
1_ADDER
- 这个是带输入的加法器vhdl代码,是带有输入端和进位的.-with imported Adder VHDL code, which is input into and spaces.
89_full_adder
- 这个是带先行进位的加法器的vhdl代码,比较复杂,仅仅供大家参考.-into first place with the addition of VHDL code more complicated, just for reference.
1.6运算器部件实验：乘法器
- 这个是用vhdl编写的乘法器,仅仅供大家参考-VHDL prepared by the multiplier, just for reference
VHDL-FPGA-clock
- ＦＰＧＡ数字钟的设计，用VHDL语言编程，max+plus仿真，可在实际电路中验证-FPGA design, VHDL programming, max plus simulation, in the actual circuit verification
vhdl
- 基于MAXPLUS II 的软件设计，这里面有几个小程序，用于VHDL的GDF设计，含有LED数码管的显示驱动程序，还有3选一，十选一程序。-II FPGA-based design software, there are several small procedures, GDF for VHDL design with a digital LED display driver of the procedures, there is a three elections. 10 election
vhdl
- VHDL 函数信号发生器 VHDL 函数信号发生器
VHDL
- VHDL（Very-High-Speed Integrated Circuit Hardware Descr iption）
ref-sdr-sdram-vhdl
- FPGA连接SDRAM的源程序，VHDL语言实现，功能基本完全。应用效果好。
a VHDL Compiler
- 这是一个VHDL（硬件描述语言）的编译器，更确切说是一个解释器，输入是VHDL语言，输出是经过提到后的符号表，也就是将VHDL中的重要变量比如输入输出变量和DFF等保存下来。-This is a VHDL (hardware descr iption language) compiler, more precise explanation is a device that is VHDL input, output was mentioned after the symbol table to
The VHDL Cookbook
- The VHDL Cookbook VHDL 教程 -The VHDL Cookbook VHDL Guide Directory
verilog vhdl编写的串并转换
- verilog vhdl编写的串并转换
dian-zhi-shizhong-vhdl-yu-yan-shiji
- 电子时钟VHDL程序与仿真包含了电子时钟设计的全部代码-good good good good good good good good good good good good good good good