FPGA/CPLD应用,uart的Verilog HDL原码-FPGA / CPLD applications, UART Verilog HDL source

这是一个用Verilog HDL和VHDL设计的UART控制器的IP核，里面有详细的源代码-This is a Verilog HDL and VHDL design UART controller IP core, which has detailed source code