搜索资源列表
ep1c20.rar
- 一个cyclone板的原理图，cyclone型号是：ep1c20f400c8,A cyclone board schematics, cyclone model is: ep1c20f400c8
Cyclone_II_FPGA_sch
- altera 飓风二代开发板的原理图，pdf格式 -altera hurricane of the second generation development board schematics, pdf format
EP3C120
- EP3C120的官方开发板原理图，cyclone iii 系列最大的FPGA.-EP3C120s official development board schematics, cyclone iii series of the largest FPGA.
Cyclone_Calc_RevWithSplineJan-2006
- 旋风分离器设计,验算模板改进的,不需查图,采用二次样条插值,并有详细说明 -Cyclone separator design, an improved check template without Chaturvedi, using quadratic spline interpolation, and a detailed descr iption
cyclone3c25
- cyclone III系列的3c25的详细例子及其讲解 对深入学习FPGA有很大帮助-very help--cyclone 3 ep3c25
CycloneIII
- 有关FPGA的AS、JTAG配置的中文资料-The FPGA-AS, JTAG configuration of the Chinese data
Bufor
- Circular buffer using a cyclone memory ( Quartus II and VHDL .)-Circular buffer using a cyclone memory ( Quartus II and VHDL .)
radar1
- 介绍了利用Altera公司的FPGA 器件 (cyclone) 产生线性调频信号的DDS工作原理、设计方案、电路结构。并详细讨论了利用FPGA 器件实现DDS技术时, 采取的一些改进优化措施-Introduced the use of Altera' s FPGA device (cyclone) generate a linear FM signal DDS working principle, design, circuit configuration. And discussed i
cycloneIII_3c120_dev_niosII_standard
- 该源码是关于FPGA片上系统sopc的nios处理器设计，他实现了led，lcd以及Internet网络各种功能，源码已经测试通过，读者可以使用-The source is on the FPGA chip on the system sopc the nios processor design, he realized the led, lcd, and Internet networking features, source code has been tested, the reader
DisasterEarlyEwarningSystem
- Disasters strike without warning. Natural calamities like flood, cyclone, earthquake or any other mishappening bring heaps of troubles on all of us. People are rendered homeless. Their properties are ruined. While many people are aware of the terribl
xiangqixuanfeng6.2
- 正版的象棋旋风象棋软件，不要错过好机会，机会难得-Genuine Tornado chess chess software, do not miss a good opportunity, a rare opportunity
DecodeHexabc
- Decoder 8bits FPGA for cyclone altera DE2-70
S_ram
- S_ram in vhdl languages in fpga chip for cyclone 2
LCD_test
- this a example for the LCD for altera FPGA cyclone ii EP2C8. implemented in verilog. tested using altera EP2C8 fpga
audio_latest.tar
- Audio Codec(ADPCM 1-Bit) The code is ready for Altera Cyclone-II DE1 Starter board and it is tested, you can modify codes and use them in any project. Core Descr iption: Sampling Frequency: 44100Hz Channels: Stereo Bit-rate: 1 Bit Per Sa
Protel99_lib_ALTERA
- protel cyclone iii系列 原理图，PCB
digital_clk
- VHDL Code for a digital bit clock counter and 7 segment display clock on a altera DE2 board with a cyclone II FPGA
cyclone-physics-master
- the source code of Game Physical Engine Development
C5中文说明手册
- cyclone v中文说明手册 使用说明书(Cyclone V Manual of Chinese instructions)
Cyclone?IV?器件手册_CN
- 英特尔飓风4中文手册第一卷和第二卷部分。(The first and second volumes)