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statemachine
- 用verilog HDL实现状态机的设计-Verilog HDL make the state machine come true
statemachine
- 这是三个状态机写法的举例,分别包含一段式状态机,二段式状态机和三段式状态机的写法-These are three examples of the wording of the state machine, contain some type state machine, state machine and the wording of the two-stage three-state machine
StateMachine
- This a sample program showing how to design and implement finite state machine(FSM).-This is a sample program showing how to design and implement finite state machine(FSM).
