I2C总线VHDL/Verilog HDL源码 通过仿真验证正确，希望对大家有用-I2C bus VHDL/Verilog HDL source code is verified by simulation is correct, we hope to useful

模拟了一个i2c通信系统，默认包括一个主机一个从机和一条总线，可以添加多个从机，最高支持7个从机-Simulates a i2c communication system includes a default host a slave and a bus, you can add multiple slaves, up to 7 slaves