搜索资源列表
sha_core
- 安全散列函数的VERILOG实现，通过了fpga验证，在系统正可以直接当IP盒应用-Secure Hash Function VERILOG achieve, through the FPGA verification, the system is can be directly applied when the IP box
Linux_bc
- 对vga接口做了详细的介绍，并且有一 ·三段式Verilog的IDE程序，但只有DMA ·电子密码锁，基于fpga实现，密码正 ·IIR、FIR、FFT各模块程序设计例程， ·基于逻辑工具的以太网开发，基于逻 ·自己写的一个测温元件（ds18b20）的 ·光纤通信中的SDH数据帧解析及提取的 ·VHDL Programming by Example（McGr ·这是CAN总线控制器的IP核，源码是由 ·FPGA设计的SDRAM控制器，有仿真代码 ·xili
AES
- AES算法的verilog代码，即AES算法IP核-ip core for AES
sha
- 内带3个sha1的C源码。经验证都可用。在我们项目中，已经用于验证SHA1的verilog-With three within the C source code sha1. Experience certificate are available. In our project, has been used to validate SHA1 of verilog
systemcaes_latest.tar
- 高级加密标准aes加密算法用fpga实现的Verilog源代码。-Advanced encryption standard aes encryption algorithm using fpga implementation Verilog source code.
SDRAM_verilog-serial-port
- FPGA对sdramd的操作，verilog语言设计！-FPGA SDRAM verilog
ucliunx
- 采用verilog语言，在fpga上实现uclinux的移植，使用nios 2 ，成功完成移植-Verilog language uclinux porting nios fpga on the successful completion of the transplant
AES-based-on-FPGA-jiami
- 该模块是基于FPGA的AES加密算法实现的Verilog代码，包含一个顶层文件和两个调用模块，最高误差在15ns-This module is the AES encryption algorithm FPGA based on the Verilog code, contains a top-level files and two call module, the maximum error in 15ns
DES-and-3DES
- 用FPGA实现的DES和3DES算法，使用开发板DE2-115通过验证-EDS&3DES based on ALTERA-FPGA,realized by Verilog HDL and DE2-115board.
FPGA-IMPLEMENTATION-OF-AN-AES-PROCESSOR
- Advanced Encryption Standard(AES) implementing in a faster and secured way is expected. AES can be implemented in software/hardware. In hardware implementation ASIC solution requires high cost and much design time while FPGA based implementation
final-project-dpim
- FPGA模块设计，包括脉冲发送，信号处理，以及接收，系统是基于windows系统，verilog语言实现。-FPGA module design, including pulse transmission, signal processing, and receive, the system is based on the windows system, verilog language。
final-project-dppm
- FPGA模块设计，包括脉冲发送，信号处理，以及接收，系统是基于windows系统，verilog语言实现-FPGA module design, including pulse transmission, signal processing, and receive, the system is based on the windows system, verilog language
press_counter
- 基于verilog 的按键计数程序，约束文件对应的是BASYS2 的 FPGA开发板，注意数码管对应的管脚分配-Press count program based on Verilog
HASH
- hash加速器的verilog实现，也用于fpga或asic-hash verilog rtl
AES
- aes源码verilog带有仿真环境，可用于FPGA实现-aes verilog rtl
pcm.tar
- 在FPGA开发板上实现通信中PCM30/32系统的时分复用，编码，解码，串并行转换，以及同步识别(On the FPGA development board, we complete time division multiplexing, encoding, decoding, serial parallel conversion and synchronization identification of PCM30/32 system in communication.)