搜索资源列表
clk-corediv
- MVEBU Core divider clock.CORE_CLK_DIV_RATIO_MASK.
clk-frac
- The clock is an adjustable fractional divider with a busy bit to wait when the divider is adjusted.
i2c-designware
- Provides clock implementations for three different types of clock devices on the Axxia device: PLL clock, a clock divider and a clock mux.
irq_impl
- clk register fractional divider for Linux v2.13.6.
imx6qdl-wandboard-revb1
- DOC: basic fixed multiplier and divider clock that cannot gate.
io_ordering
- DPLL rate rounding: minimum DPLL multiplier, divider values.
sja1000
- clock divider register.
st-clkgen-prediv
- Binding for a ST pre-divider clock driver.
mm_internal
- Binding for a ST divider and multiplexer clock driver.
sonixb
- high-nibble is sensor clock divider, changes exposure on sensors which use a clock generated by the bridge. Some sensors have their own clock.
clk-divider
- linux sound pxa2xx-ac97.c AC97 support for the Intel PXA2xx chip. -linux sound pxa2xx-ac97.c AC97 support for the Intel PXA2xx chip.
clk
- This fixups the register CCM_CSCMR1 write value. The write read divider values of the aclk_podf field of that register have the relationship described by the following table:.