搜索资源列表
SHA1_TOP
- sha_1加密运算模块，运算速率100Mbps，规格512位请大家参考-encryption algorithms sha_1 module, computing rate of 100Mbps, the specifications please refer to 512
sha1_verilog
- 安全散列算法的另一种verilog实现，对面积的要求更小，但损失了速度，但在一般系统中，完全可以满足大部分需要了-Secure Hash Algorithm another Verilog realization of the demands of a smaller area, but a loss of speed, but in the general system, fully satisfy the needs of the most
Timer
- 基于ｖｈｄｌ的电子时钟，其中包括六进制计数器和十进制计数器。-VHDL-based electronic clock, including six hexadecimal decimal counters and counters.
8086IP
- 开源CPU软核8086的源码,波兰版Verilog源码-8086 soft-core CPU revenue source, the Polish version of Verilog source code
vh2sc
- 将VHDL转换为C的软件 将VHDL转换为C的软件-VH2SC is a free basic VHDL to SystemC converter. The converter handles a small subset of Synthesisable VHDL 87/93 language constructs. The current version translates all VHDL IEEE types to sc_int/sc_uint/integers and boole
crc16
- 16bit CRC for 8bits data
DP_RAM_lab
- 用SmartGen 生成一个2k*8 Dual Port RAM，并通过串口发送数据初始化RAM。然后通过串口返回到上位机的串口调试程序显示。-SmartGen generated using a 2k* 8 Dual Port RAM, and sending data through the serial port to initialize RAM. And back through the serial port to the PC serial port debugger displ
1
- VHDL国外大学的学习资料 学习VHDL的首选参考-VHDL University study abroad information of choice for studying VHDL reference ~ ~
sha
- sha加密算法实现，经过FPGA验证的！-sha encryption algorithm, after FPGA validation!
CPU
- CPU编程，比较低层的硬件编程的 chm 资料文件--
first_cpu
- nios ii cpu核，包含通用IO口、sdram、flash、uart-nios ii cpu、genernal io port、sdram、falsh、uart
aes_crypto_core_latest.tar
- Consecutive AES core Descr iption of project.. Features - AES encoder - 128/192/256 bit - AES decoder - 128/192/256 bit Status - Key Expansion added - Encoder added - Decoder added - Documentation added
GF_MUL
- Galois域乘法器的Verilog源码 广泛用于信道编码、计算机代数及椭圆曲线加密等-Galois field multipliers are widely used in the Verilog source channel coding, computer algebra and elliptic curve encryption
crc
- CRC校验码的实现，校验码6位，寄存器串行实现方式，经项目实际验证正确-CRC Check Code realization Check 6, register serial ways, the right to verify the actual project
GeneradorCRC
- This Circuit generates the syndrome for the CRC. This is quite useful for transmision purposes and error checking issues.
3DES
- fpga3des加密非常有用 希望大家喜-fpga3des
edapiano.doc.tar
- EDA 电子琴 EDA 电子琴 EDA 电子琴 -EDA piano
khalil2006_true_random_number_generator
- a true random number generator (TRNG) in hardware which is targeted for FPGA-based crypto embedded systems. All crypto protocols require the generation and use of secret values that must be unknown to attackers.Random number generators (RNG) are requ
BasicRSA_latest.tar
- RSA ( Rivest Shamir Adleman )is crypthograph system that used to give a secret information and digital signature . Its security based on Integer Factorization Problem (IFP). RSA uses an asymetric key. RSA was created by Rivest, Shamir, and Adleman i