搜索资源列表
rom_des.zip
- DES 加密算法的VHDL和VERILOG 源程序及其TESTBENCH。
rijndaelimplemetation
- rijndael算法的一个vhdl语言编写的程序,可供学习者参考交流-a VHDL language procedures, exchange of information for learners
aldec41
- VHDL把图片移动到星号密码上密码的原形就看到啦.zip] - 程序里有一个张图片.把图片移动到星号密码上,密码的原形就看到啦 [QQ 2005贺岁版登录口令加密算法及其源代码.rar] - QQ 2005贺岁版登录口令加密算法及其源代码,请大家指教 [各cracked软件的安装方法.rar] - 各种开发用常用软件的破解安装方法 非常值得收藏的好东西-VHDL Pictures moved to the asterisk password on the password will
3des-VHDL
- 3des的VHDL实现，适用于quartus环境-3des VHDL applicable to the environment quartus
tcdg[1].vhdl
- 直接仿真就可以使用，子密钥的输出采用了优化设计，节省了资源。-direct simulation can be used, the output Subkey using the optimum design, saving resources.
aes_8bit
- VHDL实现128bitAES加密算法 LOW AREA节约成本的实现 DATA FLOW为8bits
scrambler
- 扰码程序，利用VHDL语言实现，适合各种通信系统的扰码。
des
- DES加密VHDL源代码,包括速度优先与面积优先两种设计
aes-vhdl 使用vhdl语言实现aes（rijndael 算法）
- 使用vhdl语言实现aes（rijndael 算法），程序整体封装成为一个package，方便调用-Using vhdl language aes (rijndael algorithm), the program as a whole package as a package, easy call
rom_des
- DES 加密算法的VHDL和VERILOG 源程序及其TESTBENCH。-VHDL and VERILOG sourcecode and TESTBENCH of DES encrypting algorithm
rc5statemac
- rc5 encryption- rc5 encryption using vhdl, using state machine, more detailed descr iption can be found in ieee papers.
rc5decstmac
- RC5 decryption algorithm implementation, using vhdl, with state machine implementation, use ieee papers for more detailed descr iption.
rc5keyexp
- rc5 key expansion algorithm implementation in vhdl, using state machine too. use ieee papers for more detailed descr iption
tripledes
- 3-DES加密IP核VHDL源码，3次DES流水执行-VHDL source code for 3-DES encryption IP core, pipelined execution
rsa
- 用VHDL求rsa加密系统的密钥D（辗转相除法）-Using VHDL for rsa key encryption system D（Division algorithm）
freehdl-0.0.6.tar
- inplementation of AES vhdl The use of a list of law, VHDL language based polynomial-based finite field multiplier, for the AES algorithm
topic
- DES加密算法的VHDL和VERILOG源程序- Xilinx开源共享61EDA代码工厂-DES encryption algorithm of VHDL and VERILOG source code- Xilinx factory open source code sharing 61EDA
AES
- 详细描述了AES加密算法的过程及S盒变换，用VHDL语言描述，通俗易懂-AES encryption algorithm is described in detail the process and transform S box, with the VHDL language to describe, easy to understand
vhdl-implementation-of-advanced-encryption-standa
- vhdl implementation of advanced encryption standard algorithm
aes_thesis_v1.0
- aes code in verilog vhdl language which is very useful.