搜索资源列表
AES
- AES算法的verilog代码，即AES算法IP核-ip core for AES
mini_aes_latest[1].tar
- AES 加解密 代码, 有文档说明，testbench-AES encoding decoding source code in HDL
hundunjiami
- 混沌加密应用于实际电路的VHDL语言编写的电路选通程序。-Chaotic encryption used in the actual circuit of the circuit VHDL language gating process.
t3_enc
- triple des encryption decryption
Booth_Multiplier
- 布斯乘法器,适用于VHDL语言操作,对于初学者或是深入的人都适宜-Booth Multiplier
jtag
- JTAG Tools is a software package which enables working with JTAG-aware (IEEE 1149.1) hardware devices (parts) and boards through JTAG adapter. This package has open and modular architecture with ability to write miscellaneous extensions (like b
costas
- 科斯塔斯载波同步的实现。采用了V_LOG代码编写~~~~ 可以直接编译使用-Costas carrier synchronization is achieved. Coding used V_LOG ~ ~ ~ ~ can direct the compiler to use
beipin
- 倍频出200M时钟，对输入脉冲进行计数测量时间间隙-produce 200M clock，count the input pulse
AESsim
- AES alogrithm security encryption
80300di
- this a vhdl program for crc encoder and decoder-this is a vhdl program for crc encoder and decoder
dsp_radar
- radar detecttion in verilog
HAMMING_ECC
- HAMMING ECC，1 BIT ERROR CORRECTION， 2 BITS ERROR DETECTION -HAMMING ECC，1 BIT ERROR CORRECTION， 2 BITS ERROR DETECTION
DESCryptographicAlgorithm
- des加密算法,用于IP通讯方面的,用VHDL写成的源程序-des encryption algorithm used for IP communications.the source codes are written in VHDL
use_3_shoft
- SHA-1的verilog程序，经过优化的了，希望可以对大家有帮助-SHA-1 of the verilog program, optimized, and hope that we can help you
Crc_Parallel
- CCITT Parallel CRC 16-bit
Euclidean_divider
- This the euclidean algorithm implementation in VHDL -This is the euclidean algorithm implementation in VHDL
des3
- The best 3des code. The best area
aes128
- AES实现的效率如面积、吞吐量和功耗等，主要是由列混合变换和S 盒的实现决定的。S 盒单元的实现成为设 计的重点，它的硬件实现在很大程度上决定着整个芯片的面积大小。 -AES to achieve efficiency, such as area, throughput and power consumption, mainly by the S box column mixing transformation and the realization of decision. S box
systemcaes_latest.tar
- 高级加密标准aes加密算法用fpga实现的Verilog源代码。-Advanced encryption standard aes encryption algorithm using fpga implementation Verilog source code.
RSB.RAR
- Realization criptography algoritm on VHDL Round step block