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weisuiji
- 伪随机码系统器件发生器 产生伪随机序列 使用VHDL 语言开发设计，编写长度不长，只有20多行-Pseudo-random code system device generator produces pseudo-random sequence using VHDL language development and design, write the length is long, only 20 more lines
vhd
- 这是我的vhdl课程资料 绝对独家 绝对有用 大家用啊1-IT‘s very good！
RC4
- This the most efficient cookbook for understanding VHDL-This is the most efficient cookbook for understanding VHDL
AESvhdl
- AES vhdl, encryption, decryption code
Advanced-Encryption-Standard-(AES)
- AES decryption standards, vhdl code
3des_vhdl
- 3DES算法VHDL实现，适用于XILINX FPGA-3DES algorithm VHDL Implementation，fit to XILINX FPGA
PS_2
- PS_2接口VHDL代码，与开发板配合使用，经过测试可以用-PS_2 interface VHDL code, tested can be used in conjunction with the development board
FIR
- an FIR code which is writen in vhdl. this entity has clk and reseet inputs, and the filter output is provided as well. the coefficients of the filter are passed using a set of constants.
NOC
- a vhdl code for an noc switch, which is a set of 3*3 array of noc switches and each switch has a buffer to store the incoming data.
FIFO
- a fifo designed in vhdl. this fifo is implemented in a different way, using access type.
aes_imp
- AES CODE IN VHDL FOR ENCRYPTION AND DECRYPTION
codeVHDL
- code vhdl for encrypt and dencrypt aes
carryGP
- carry look ahead adder code for vhdl subscribe
biCounter
- Counter programs for vhdl subscr iption
ViterbiDecoder
- Viterbi decode in VHDL
SERPENT
- serpent vhdl sample code
work
- Grain stream cipher VHDL code
eli0011
- 基于VHDL的IIR滤波器设计 用并行处理有耗积分器III的形式设计的二阶IIR巴特沃斯低通数字滤波器 -VHDL-based IIR filter design with parallel processing of lossy integrator III design in the form of second-order IIR Butterworth low-pass digital filter
seven_seg
- 环境VHDL,工具quartusII,结合EDA实现，实现功能七段扫描显示-Environmental VHDL, tools quartusII, combined with EDA, achieving functional segment scan display
aes_crypto_core_latest.tar_2
- VHDL CODE FOR AES CRYPTO CORE