搜索资源列表
md5_latest[1][1].tar
- MD5算法verilog代码，很不错的，可以互相交流学习-MD5 algorithm verilog code, and a very good
crc1
- CRC编码verilog代码，用于实现crc编码功能-CRC coding Verilog code for CRC encoding capabilities to achieve
btm_crc_crc32_8
- 自己项目用到的crc32-8源程序，btm校验。-Used their own projects crc32-8 source, btm checksum.
sha256_512
- Verilog实现的SHA256/SHA512算法，已仿真和验证-Verilog implementation of SHA256/SHA512 algorithm, simulation and verification has been done.
crc16
- 16bit CRC for 8bits data
DP_RAM_lab
- 用SmartGen 生成一个2k*8 Dual Port RAM，并通过串口发送数据初始化RAM。然后通过串口返回到上位机的串口调试程序显示。-SmartGen generated using a 2k* 8 Dual Port RAM, and sending data through the serial port to initialize RAM. And back through the serial port to the PC serial port debugger displ
fpadd
- 利用verilog hdl编写的浮点加法器运算单元，单精度。-Verilog hdl prepared to use floating-point adder computing unit, single-precision.
sha
- sha加密算法实现，经过FPGA验证的！-sha encryption algorithm, after FPGA validation!
first_cpu
- nios ii cpu核，包含通用IO口、sdram、flash、uart-nios ii cpu、genernal io port、sdram、falsh、uart
GF_MUL
- Galois域乘法器的Verilog源码 广泛用于信道编码、计算机代数及椭圆曲线加密等-Galois field multipliers are widely used in the Verilog source channel coding, computer algebra and elliptic curve encryption
crc
- CRC校验码的实现，校验码6位，寄存器串行实现方式，经项目实际验证正确-CRC Check Code realization Check 6, register serial ways, the right to verify the actual project
crc7
- crc7 calculation for SDIO mode
CRC_Rx
- 本设计为CRC5接收效验模块。本设计模块用来接收数据的CRC效验。本模块共需要5个时钟周期来完成：-CRC5 designed to receive this well-tested modules. The design module used to receive data CRC effectiveness. This module needs a total of 5 clock cycles to complete:
AES
- AES算法的verilog代码，即AES算法IP核-ip core for AES
SMS4_1.0
- 本项目将一组128位主密钥0123456789abcdeffedcba9876543210（16进制）通过4轮密钥扩展，获得前4轮子密钥，4轮子密钥再通过数码管分8批按16进制循环显示，该4轮子密钥理论值应为： f12186f9 41662b61 5a6ab19a 7ba92077. 所以8批数码显示数据应为： 86f9 f121 2b61 4166 b19a 5a6a 2077 7ba9. -A group of the project will be 128-bit mast
costas
- 科斯塔斯载波同步的实现。采用了V_LOG代码编写~~~~ 可以直接编译使用-Costas carrier synchronization is achieved. Coding used V_LOG ~ ~ ~ ~ can direct the compiler to use
beipin
- 倍频出200M时钟，对输入脉冲进行计数测量时间间隙-produce 200M clock，count the input pulse
aes_core
- aes_core verified verilog ip core-aes_core verified verilog ip core
cpu
- sopc 中的cpu软核，可以配置成soc,成为片上可编程系统-sopc in soft-core cpu, can be configured into a soc, as a programmable system chip
Sensor
- file for sensor data collection