搜索资源列表
crc5
- crc5为5位的数据校验码，起着检测数据正确与否的功能~-crc5 5 data validation code plays a test data is correct or not the function ~
ps2_mouse_top
- ps2鼠标顶层模块电路，仅仅包括顶层不含其他。-ps2 mouse top-level module circuit, and only include the top level without other.
decrypt_timing-simulation
- 用VC6.0实现的aes解密时序仿真-Use the VC6.0 realization of the aes decryption timing simulation
aes_highthroughput_lowarea_latest.tar
- low area aes encryption system
c499
- sec code 电路，用于纠错检错和错误恢复的功能，verilog描述。-sec code circuit, for correction of error detection and error recovery functions, verilog descr iption.
wang
- 信号监测器 用状态机对二进制码1100进行检测-Uses state of the signal monitoring to detect the binary code 1100
ASDU1_4000
- dm6467的驱动源码 针对网络层的驱动 简易 的C语言 值得收藏-dm6467 driver source code for easy drive of the network layer of the C language worthy of collection
aFIFO
- 实现了一个异步fifo功能的verilog模块-An asynchronous fifo function verilog module
pcie_top
- verilog pcie for pcie design-verilog pcie
DE2-DES-decryption
- 视频图像的加密与解密，完全硬件实现，DE2板子实现，实时效果非常好-The encryption and decryption of video images, fully implemented in hardware
eightV2
- 八位加法器源代码，大学计算机原理实验要求要用的 要的就来把-Eight adders source code, School of Computer principle experiment requires use to come to
d10-counter
- 十位加法器，用verilog语言编写，适用于verilog学习。-10-bit adder, using Verilog language, applicable in verilog learning.
clk-10divide
- 十分频，用verilog语言编写的程序，使用与verilog学习。-The very frequency, the Verilog language program, the use of learning verilog.
rtl
- advanced encryption standard algorithm implementation
nios_12864
- 基于FPGA的频率计设计，用12864液晶屏显示-FPGA-based frequency meter, 12864 LCD display
Dima-Blowfish
- Blowfish, verilog HDL, synthesable
aes_ashok128
- aes128 bit encryption
jiaotongdeng
- 运用verilog实现交通灯控制，从而模拟十字路口的交通状况-Use verilog to control traffic lights, thus simulating the crossroads of traffic conditions
02_interface
- 蓝色经典版EP2C5,FPGA接口实验程序-FPGA interface
AES-based-on-FPGA-jiami
- 该模块是基于FPGA的AES加密算法实现的Verilog代码，包含一个顶层文件和两个调用模块，最高误差在15ns-This module is the AES encryption algorithm FPGA based on the Verilog code, contains a top-level files and two call module, the maximum error in 15ns