搜索资源列表
DES-and-3DES
- 用FPGA实现的DES和3DES算法，使用开发板DE2-115通过验证-EDS&3DES based on ALTERA-FPGA,realized by Verilog HDL and DE2-115board.
ldpc-decoderVHDL
- 采用VHDL实现LDPC码的编解码过程，有一定的参考价值，希望对大家有帮助-Use VHDL to realize the decoding process of LDPC code has a certain reference value, hope to help everyone
postpro
- 真随机数发生器后处理方法，冯诺依曼纠偏法。-true random number generator, postprocess
dec_data.v.tar
- This the Dataflow Model of decoder.-This is the Dataflow Model of decoder.
TIMER_test
- DSP6713的定时器测试程序，包括FPGA的接口程序，DSP与FPGA协同工作。-DSP6713 timer test program, including the FPGA interface program, DSP and FPGA to work together.
wz_aes
- 128位AES加密算法的实现，其中具体的完成了AES加密算法的基本功能。-128-bit AES encryption algorithm to achieve, which completed the basic functions of specific AES encryption algorithm.
wz_inv_aes
- 这里包含了128位AES加密算法的整个解密过程，准确无误的完成了整个解密过程。-This contains the entire decryption process 128 AES encryption algorithm, accurate completion of the entire decryption process.
final-project-dpim
- FPGA模块设计，包括脉冲发送，信号处理，以及接收，系统是基于windows系统，verilog语言实现。-FPGA module design, including pulse transmission, signal processing, and receive, the system is based on the windows system, verilog language。
final-project-dppm
- FPGA模块设计，包括脉冲发送，信号处理，以及接收，系统是基于windows系统，verilog语言实现-FPGA module design, including pulse transmission, signal processing, and receive, the system is based on the windows system, verilog language
ECDSA
- ECDSA加入SHA1的Verilog實現,以system.v連結-ECDSA join SHA1 of Verilog implementation to system.v link
press_counter
- 基于verilog 的按键计数程序，约束文件对应的是BASYS2 的 FPGA开发板，注意数码管对应的管脚分配-Press count program based on Verilog
rtl_wangjiangxing
- ecc椭圆算法RTL,verilog经过验证-ecc verilog
HASH
- hash加速器的verilog实现，也用于fpga或asic-hash verilog rtl
MyPeripheral_test
- 基于ZedBoard开发板zynq7000处理器，各种外设的操作和控制的工程源码（包括GPIO/中断/看门狗/EDMA/OCM/定时器等）。-A project source based on the zynq7000 SOC of Zedboard development kit，all kinds of peripheral test（including GPIO/interrupt/WTD/EDMA/OCM/timer .etc）.
MyIPCore_test
- 基于ZedBoard开发板的zynq7000系列芯片，通过PS调用PL的IP核的样例。该IP核可以控制ZedBoard开发板上的8个LED和5个开关。-ZedBoard based development board zynq7000 series chip, the sample of PS calling PL IP core. The IP core can control ZedBoard development board 8 LED and 5
AES
- AES encryption and decryption
cnt10
- vireloge实现pwm波形发生器 用四个模块实现 十进制计数器-Veriloge pwm waveform generator designed to achieve decimal counter
trunk
- 用Verilog语言仿真3种NoC中路由器的实现流程，验证其性能。-Simulation of 3 kinds of NoC routers in the implementation process of the Verilog, verify its performance.
present80
- present80算法实现，verilog 代码实现-present80 algorithom implementation
thermometer
- 温度译码器，设计一个4-15thermometer (温度计）译码器电路，以及将译码后输出的信号同步后串行输出。-Temperature decoder