搜索资源列表
mtech-pr3-conventional-lms
- adaptive LMS algorith for modified approach
aes__code_based_on_verilog
- AES核心代码，用verilog写的，可供参考-aes core code using verilog for learning
DECODE
- 解码，进行解码操作。很好用运行成功，可以下载。-Decoding, decoding operation. Good use is running, you can download.
aes
- 使用verilog的128位aes加密源程序-Use verilog of 128 aes encryption source code
clock171
- 电子时钟，能够进行计时，可设定闹钟，可以当做跑表，并且可以更改时间-electric clock
rc4_crypt
- 自己写的rc4加解密算法部分的verilog代码，可综合，供大家参考-Write your own encryption algorithm verilog codes rc4 section can be integrated, for your reference
xapp270
- The xilinx application nnote source code DES encryption and decryption
SM4-in-single-Feistl-Iteration
- 单轮迭代结构SM4算法实现，该电路结构通过一个复合域轮函数的迭代实现整个SM4加密过程，具有非常小的资源消耗。-Single iteration structure SM4 algorithm, the circuit structure achieves the entire encryption process SM4 domain by iterating a complex round function, with a very small resource consumption.
aes_t1
- 对aes加密过程的详细描述,字节替换，行移位，列混合等-Detailed descr iption of the aes encryption process, byte substitution, shift rows, columns, mixing, etc.
fuuladder.v
- this a fulladder in verilog-this is a fulladder in verilog
zy
- 它包含UART发送器，发射器波特率发生器，接收 波特率发生器，一共有四个模块。包括四个文件：speed_select.v，my_uart_rx.v，my_uart_tx.v，my_uart_top.v。设计包含UART发送器、发送器的波特率发生器、接收器、接收器的波特率发生器，共四个模块实现。包括四个文件: speed_select.v, my_uart_rx.v, my_uart_tx.v, my_uart_top.v。 my_uart_rx：完成数据的接收； speed_rx：响应m
AES_VeriLog
- AES Algorithm in Verily
poly.tar
- bch polynomial multiplier
des
- verilog实现des的加密解密源代码-verilog realization of des encryption and decryption source code
iic
- 通过iic时序的控制以及其读写，进行相应的设计-Through the iic timing control and their reading and writing, the corresponding design
aes_encryption
- AES 加密算法, 可综合的 verilog代码-AES encryption algorithm, synthesizable verilog codes
ad9854_drive_64bits
- ad9854 verilog程序代码,初学者编辑，上传供大家学习参考-ad9854 verilog code, for beginners to edit, upload for everyone to learn reference
cv_soc_tse_ed.tar
- 三太以太网的基础模板，可以一次为基础，进行二次开发。-three ethernet
UART
- 串口调试程序，已调试成功，望采纳！串口传数据准确无误-Serial debugger, debugging has been successful, hope to adopt!
DES_orginal_core
- this a DES encryption code in verilog-this is a DES encryption code in verilog