搜索资源列表
PUF_TRNG
- this a verilog code of true random number generator using butterfly puf-this is a verilog code of true random number generator using butterfly puf
creat_pwd
- 密码穷举，可穷举0-9，a-z共36个字符- U5BC6 u7E1 u7E1 u7E7 u4E3E uFF0C u53EF u7A77 u4E3E0-9 uFF0Ca-z u517136 u4E2A u5B57 u7B26
Chapter14
- FPGA 信道的加密与解密，文件有工程实例，直接打开运行即可 -Quot u1 " U53EF
Chapter15
- CRC编码，文件里工程实例，打开后，，里面有QPF后缀的文件，直接运行即可-CRC u7801 uFF0C u6587 u4EF6 u91C u5DE5 u7A0B u5B9E u4F8B uFF0C u6253 u5F00 u540E uFF0C uFF0C u91CC u9762 u6709QPF u540E u7F00 u7684 u6587 u4EF6 UFF0C u76F4 u63A5 u8FD0 u884C u5373 u5
code_test
- uvm testbench 例子，可以在questa软件里运行，运用shell脚本，在cygwin环境中执行，非常方便-Uvm testbench example, you can run in questa software, the use of shell scr ipt, in cygwin environment, very convenient
aes_thesis_v1.0
- aes code in verilog vhdl language which is very useful.
des
- DES in verilog codes
ENCODE_8B_10B
- 8B_10B编码器FPGA设计,平台上验证，结果可用。(Design of FPGA encoder 8B_10B,reading out crc after calculating the value.)
AES-GF(2^4)^2 for sbox
- AES加解密程序，128bit数据位宽，其中sbox和混合列运算在复合域GF(2^4)^2上完成(An AES encryption and decryption program with 128 bits datawidth, which used GF(2^4)^2 for sbox and mixcolumn.)
aes_GF(2^4)^2 for sbox
- AES加解密程序，128bit 数据位宽，其中加密部分的sbox采用复合域GF(2^4)^2运算(An ARS program with 128bits datawidth, which used GF(2^4)^2 for sobx in cipher.)
rtl
- 实现sha1（128）杂散算法。输入为64bit，输出160bit。(Implementation of SHA1 (128) algorithm. The input is 64bit, and the output is 160bit.)
src
- 用于国密4的加解密算法实现，采用verilog 语言，可进行vivado仿真，vivado版本是2013，结果经测试正常，适合从事相关行业的工作人员进行借鉴和开发。(The code is realized and simulated by verilog. The simulation result has been confirmed by the author. It is recommended to download by the researchers who are in the
VGA_CLK
- 电脑屏幕显示时钟，以及闹钟特效，动态显示图片的特效(Computer screens, clocks, and alarm clocks)
etzgrtise-create
- VHDL编程 out std_logic -- Transmitter control DataBits in st()
verilog 代码
- 8位串转并，并转串verilog代码，代码+testbeach文件(The 8 bit is connected, and the Verilog code is transferred.)
antribute-squar
- turbo码_verilog_编码源文件()
Divider
- 用Verilog HDL语言实现分频器，初学，简单(The realization of frequency divider in Verilog HDL, Elementary learning is simple)
aes enc
- latest aes encryption
529623
- 实现一个用于CDMA2000系统的短帧交织器,计算比较了12 16,13 15,14 14三种交织形式的性能!()
760021
- 最近在做毕设,ldpc码的编解码实现,这个是verilog实现,()