搜索资源列表
sha1_v01.zip
- SHA-1加密算法的IP核，内涵文档，仿真测试文件,SHA-1 encryption algorithm of the IP core, the connotation of documents, simulation test file
md5_latest[1][1].tar
- MD5算法verilog代码，很不错的，可以互相交流学习-MD5 algorithm verilog code, and a very good
subbyte128
- AES算法中Sbox映射Verilog源代码，采用一一映射的方案，用查找表的方式实现Sbox。转换数据长度为128bit。-Sbox mapping Verilog source code of the AES algorithm, using one to one mapping of the program, using a lookup table to achieve the Sbox table. Convert the data length is 128bit.
rtl
- advanced encryption standard algorithm implementation
VITERBI
- viterbi编码算法verilog实现-viterbi encoder, developed by verilog language
present80
- present80算法实现，verilog 代码实现-present80 algorithom implementation
fuuladder.v
- this a fulladder in verilog-this is a fulladder in verilog
AES_VeriLog
- AES Algorithm in Verily
Chapter14
- FPGA 信道的加密与解密，文件有工程实例，直接打开运行即可 -Quot u1 " U53EF
Chapter15
- CRC编码，文件里工程实例，打开后，，里面有QPF后缀的文件，直接运行即可-CRC u7801 uFF0C u6587 u4EF6 u91C u5DE5 u7A0B u5B9E u4F8B uFF0C u6253 u5F00 u540E uFF0C uFF0C u91CC u9762 u6709QPF u540E u7F00 u7684 u6587 u4EF6 UFF0C u76F4 u63A5 u8FD0 u884C u5373 u5