搜索资源列表
asfifodesign
- 异步fifo设计文档，里面包括详细的verilog设计方案及代码。fifo设计是通信中必然设计的设计-a fifo design with code inside, using verilog language
uart16550
- uart16550 is a 16550 compatible (mostly) UART core. The bus interface is WISHBONE SoC bus Rev. B. Features all the standard options of the 16550 UART: FIFO based operation, interrupt requests and other. The datasheet can b
bulkloop
- EZ-USB FX2 SLAVE FIFO模式固件代码-EZ-USB FX2 SLAVE FIFO mode firmware code
51_uart_fifo51
- 51_uart_fifo51 串口收发程序源代码 环形缓冲区实现-Serial transceivers to achieve ring buffer source code
fifo
- fifo buffer in vhdl, first in first out in vhdl, vhdl code
fifo2
- 一种简单的FIFO的verilog代码，有利于理解FIFO的工作原理-code of fifo in verilog
trans_and_delete
- 1/2,3/4可配置的卷积码编码，其中需要用要FIFO的IP核-1/2, 3/4 convolutional code encoder can be configured with a FIFO wherein IP core
xfft_v3_2_pipe_64
- vhdl ifft and fifo code with xilinx ip core to implement OFDM Basisband-vhdl ifft and fifo code with xilinx ip core to implement OFDM Basisband
SLAVE-FIFO-16BITS
- CY7C68013a的slavefifo的固件源代码，keil编写，以及使用FPGA向EP6端点写数据的verilog源代码，没有错误，可以编译成功!-CY7C68013a of slavefifo firmware source code, keil prepared using FPGA and write data to the endpoint EP6 verilog source code, no errors, you can compile successfully!
gpif_to_extfifo-fifo-rw
- USB GPIF 接口编程源码，经过验证-The source code for USB GPIF. It was verifed.
CYUSB3014 Example Code
- Slave fifo 4 flags example