搜索资源列表
USB2.0_rtl_ipcore_verilog
- 经过门级网单验证的USB2.0 IP核 RTL代码-net after gate-level verification of USB IP Core RTL code
FPGAdatatransport
- 本文设计的FPGA模块需要对GPS、便携打印机和串口数据进行处理,将详细介绍如何设计FPGA和不同外设之间的数据传输。同时,在RTL编码中,编写使综合与布局布线效果更佳的代码。
bluetooth.tar
- 蓝牙的一个ip RTL 核,不知道对大家有没有用?谢谢。-this is an IP core of blutooth.
USB2.0
- USB2.0行为级描述,挂接在AMBA AXI总线上-USB2.0 RTL discr iption
usb1.tar
- usb1.1 完整代码, 包含 PHY 等所有的 代码 已经在 VCS, NCSIM 的环境下仿真过了,-usb1.1 full rtl and test
or1200_uart
- OR1200最小系统,包括软核处理器OR1200,内存,总线,GPIO及UART的RTL实现。在SOPC2000硬件平台上实现。软件开发环境为Ubuntu,能实现SOPC2000和PC机的简单串口通信。-OR1200 minimum system, including soft-core processor OR1200, memory, bus, GPIO and UART of the RTL implementation. In SOPC2000 hardware platform. So
ethmac10_100M
- 以太网IP Core 它实现10/100 Mbps的MAC控制器功能。它是在IEEE802.3和802.3u 标准下设计实现的。-The Ethernet IP Core is a 10/100 Media Access Controller (MAC). It consists of a synthesizable Verilog RTL core that provides all features necessary to implement the Layer 2 protocol of
uart16550_latest.tar
- UART16550是较为通用的串口协议,压缩包内有4个文件可供选择,直接提供RTL源码,可直接导入到工程内。-Uart16550 core is used for Serial Commuication.There are 4 folders in the zip package and have the verilog RTL which can be added in the project.
SDRAMverilog
- SDRAM verilog 串口实例 带有RTL图 及详细的注释-SDRAM verilog RTL serial examples with diagrams and detailed notes
mdio_vip
- MDIO验证的VIP,包含slave和master,slave和master可以接在一起进行仿真,不需要连接RTL-MDIO validation VIP, includes slave and master, slave and master can be connected together to simulate no connection RTL
RX_EQU
- OFDM系统均衡器的RTL级设计,采用了MMSE检测算法,复杂度降低-OFDM system equalizer RTL design, using MMSE algorithm complexity is reduced
gsm_ddc
- 基于GSM的数字下变频代码,能够直接生成Verilog代码,需要Synplify DSP 支持。-GSM DDC code. This Model can directly generate RTL code via Synplify DSP.
BPSK_receiver
- BPSK接收机设计,能够通过Synplify DSP直接生成Verilog代码。-BPSK Reciver model. This simulink model can generate RTL code via Synplify DSP.
RDSigGen
- 北斗一代信号源RTL源代码,可以生产RDSS中频数字信号。-RTL source code for BD1 signal.
RS485_Revc
- rs485 receive end verilog rtl code
Master SPI的Verilog源代码(包括文档 测试程序)
- SPI接口的从机实现(利用verilog HDL语言)(Slave implementation of SPI interface (using Verilog HDL language))