搜索资源列表
uart_verilog_v1
- uart d的verilog 程序，可以实现普通串口功能-UART d Verilog procedures can be achieved ordinary serial port function
usb_ctr
- usb的verilog 代码。对理解usb的原理有很大帮助，并可以在nc环境下仿真。-usb the Verilog code. Usb to understand the principle is very helpful, and to be nc simulation environment.
EP2C8_pll_example.rar
- EP2C8 PLL例化的例子,给不会的人做个参考.专门写的一个.呵呵.不过是Verilog的.,EP2C8 PLL cases of the examples to those who will not be a reference. Specialized write a. Ha ha. But the Verilog.
GSM_DDC
- GSM中数字下变频器的matlab辅助设计，并可以采用matlab生成verilog代码。-GSM digital down converter in the matlab-aided design, and can be used matlab generate verilog code.
UART
- Verilog实现的UART程序，用ISE打开工程文件即可-Verilog implementation UART program, open the project file with the ISE can be
uart16550_latest.tar
- UART16550是较为通用的串口协议，压缩包内有4个文件可供选择，直接提供RTL源码，可直接导入到工程内。-Uart16550 core is used for Serial Commuication.There are 4 folders in the zip package and have the verilog RTL which can be added in the project.
async_receiver
- 用于RS232串口接收数据的verilog语言，时钟速率可改，可直接调用。- ON划词翻译ON实时翻译 Serial port for receiving data of the Verilog language, can be called directly.
AD6643_test
- verilog实现AD6643芯片的驱动，用200MHz采样率对A、B两路信号进行采样，可以在chipscope中观察到A路和B路的数字信号，已验证程序正确可用。-Implemented in verilog language AD6643 chip driver with 200MHz sampling rate of A, B two-way signals are sampled can be observed A and B road in chipscope digital signa
receive_spi
- verilog语言SPI通信，可用于CPLD以及FPGA-Verilog language SPI communications, can be used for CPLD and FPGA
RS232
- rs232串口通讯Verilog源码，可直接用于芯片之间的串口通讯-rs232 serial communication Verilog source code can be directly used for serial communication between chips
USB-IPcore-Verilog
- USB IP 核设计，Verilog，ISE工程可以打开-USB IP core design, Verilog, ISE project can be opened
verilog_422
- 标准RS422 Verilog源代码， 传输波特率可以修改， FPGA上可以工作-Standard RS422 verilog communication source code, buardrate can be updated and it is fully work in FPGA
CH04_GTP_TEST
- GTP IP核，高速通信必须学习的部分。(GTP IP kernel, part of high-speed communication that must be learned.)
FpgaMskDemod
- 能够实现MSK的解调，语言为verilog(MSK demodulation can be achieved, and the language is Verilog.)
BtoC
- 文件中有两种方法实现并串转换模块代码的编写，可以在modelsim软件中正确仿真(There are two methods in the file to achieve the serial conversion module code writing, can be correctly simulated in Modelsim software)