搜索资源列表
Uartmodule
- 实现FPGA与PC机的串口通信功能，实现数据的收发。-FPGA with the realization of PC-serial communication functions to send and receive data.
uart
- 通用穿行通信控制器，可以直接使用，在quartsII下开发-GM through communications controller, can be directly used in developing quartsII
bpsk2
- 介绍qpsk解调的代码！初学者可以参考参考！比较简单.-Introduction QPSK demodulation code! Beginners can refer to reference! Relatively simple.
eetc_gps_all_01
- 一本全面简绍GPS的书籍,包括芯片产品，方案，厂商，产品的选型等等方面，是电子工程师在对GPS入门及产品选型不可多得的好书。-A comprehensive GPS Shaozeng Jane books, including products, programs, vendors, product selection, etc., an electronic engineer in the GPS Introduction to Product Selection and rare books
UART
- 使用方法： uart编程,拷贝到硬盘，用ISE打开工程文件即可-Usage: uart programming, copied to the hard drive, open the project file with ISE can
cpldpcvhdl
- cpld与pc机通信的VHDL代码，用于模拟cs232收发功能-CPLD with VHDL communication pc machine code, used to simulate the transceiver function cs232
psktodpsk
- psk to DPSK conversion (absolute phase shift keying to the relative phase shift keying conversion)
USB
- USB 设计（包括一个参考设计，和标准U盘）-USB design (including a reference design, and standards for U disk)
uart
- 串口通讯rs232,时钟频率为40Mhz,波特率为19200,没有奇偶校验,在xilinx XC3S200A板子上验证过.-Serial communication rs232, clock frequency of 40Mhz, the baud rate to 19200, no parity, in the board on xilinx XC3S200A verified.
filter
- 时钟滤波器设计，可进行毛刺去除，有需要可依进行参考设计-Clock filter design can be carried out burr removed, there is a need-based reference design
pro104_uart
- uart的代码，经实际运行可以通信，是xilinx uart 代码的改进，网上的xilinx uart代码有很多bug，用此代码可以改进运行。-UART code, the actual operation can be communication, xilinx uart code are improved, xilinx uart code online has a lot of bug, the code can be improved with this operation.
USBipcore
- usb1.1 ip核，使用verilog编写-usb1.1 ip nuclear, prepared using the Verilog
ps110
- bpsk信号调制，用于产生一种雷达信号。-BPSK signal modulation, used to generate a radar signal.
USB2.0FPGAEXAMPLES
- 用于USB20芯片CY7C68013和FPGA之间的通信-comunication between USB and FPGA
pcm
- information about PCM
CY7c68013_fpga_write_sram
- FPGA自FX2 slavefifo中读取数据，写入至SRAM-FPGA since FX2 slavefifo read data, write to the SRAM
c_a
- GPS中C/A码产生简单的Verilog逻辑产生-GPS in the C/A code generated simple logic generated Verilog
ldpc
- 最近在做毕设，ldpc码的编解码实现，这个是verilog实现。-Recently completed the set up to do, ldpc code codec implementation, this is the Verilog implementation.
bluetooth.tar
- 蓝牙的一个ip RTL 核，不知道对大家有没有用？谢谢。-this is an IP core of blutooth.