搜索资源列表
rei2c
- 用VHDL编写的quartusii平台上的串行EEPROM配置读取的程序。-Quartusii prepared using VHDL platform to read the serial EEPROM configuration procedures.
the_code_of_qam_modulation_demodulation
- 实现qam调制解调 实现qam调制解调-qam modulation and demodulation
DDR_interface
- 高速DDR存储器数据接口设计实例. 1. 将文件拷入硬盘 2. 产生DQS模块 3. 产生DQ模块 4. 产生PLL模块 5. 拷贝以上步骤生成的文件到子目录【Project】中 6. 打开子目录【Project】中的DataPath.qpf工程，设计顶层模块 7. 编译并查看编译结果 -High-speed DDR memory interface design data. 1. Copyed into the document hard disk 2. DQS
usb_funct
- USB 2.0 verilog源代码,内包含详细文档资料。-USB 2.0 verilog source code, which contains detailed documentation.
RS232_Controller
- This project is a RS232 Controller used to communicate two devices.
chuankoutongxin
- 串口通信的概念非常简单，串口按位（bit）发送和接收字节。尽管比按字节（byte）的并行通信慢，但是串口可以在使用一根线发送数据的同时用另一根线接收数据。它很简单并且能够实现远距离通信。比如IEEE488定义并行通行状态时，规定设备线总常不得超过20米，并且任意两个设备间的长度不得超过2米；而对于串口而言，长度可达1200米。典型地，串口用于ASCII码字符的传输。通信使用3根线完成：（1）地线，（2）发送，（3）接收。由于串口通信是异步的，端口能够在一根线上发送数据同时在另一根线上接收数据。其
MTK6225CMS2131ADF
- 联发科产品资料,包括原理图和产品外观，引脚说明等-mtk product
uart_controler_0622
- 自己设计的串口数据格式转换模块，转换格式为8位——32位，用户可自行修改。-Design their own serial data format conversion module, the conversion format for 8- 32 spaces, users can modify their own.
RS_Verilog
- RS码的FPGA实现，verilog语言形式，好参考资料-FPGA realization of RS code, verilog language form, a good reference
viterbi
- 一个vitrtbi算法的参考实现,verilog的-A reference implementation vitrtbi algorithm, verilog of
A.Software.Defined.GPS.and.Galileo.Receiver
- Software-defined radios (SDRs) have been around for more than a decade. The first complete Global Positioning System (GPS) implementation was described by Dennis Akos in 1997. Since then several research groups have presented their contribution
encode_finish
- Turbo码编码器的encode最上层模块，它的主要作用是连接Turbo码编码器的其他模块-Turbo code encoder encode top-level module, its main role is to connect the Turbo Code encoder other modules
CPLD_USB
- ：CPLD 可编程技术具有功能集成度高、设计灵活、开发周期短、成本低等特 点。介绍基于ATMEL 公司的CPLD 芯片ATF1508AS 设计的串并转换和高速 USB 及其在高速高精度数据采集系统中的应用-: CPLD programmable technology with a high degree of functional integration, design flexibility, short development cycle, and low cost. ATMEL-b
Integral_comb_filter_verilog_design
- 积分梳状滤波器(CIC)verilog设计.rar-Integral comb filter verilog design.rar
GPS_ANTIJAMMING
- GPS的干扰样式研究，具有很高的研究参考价值-GPS jamming style of research, the study of high reference value
VLSIrfid
- VLSI implementation of RFID
Bch15_5
- example of codec BCH(15,5)
uart_module
- 实现精简的uart串口,格式起始位+8bit数据位+可配置的奇偶校验位+停止位-implement a smart UART interface
CTL_SendTest
- UWB（超宽带）发射端代码控制，主管各个模块的连接和设置-UWB (ultra wideband)-side code to launch control, in charge of connecting the various modules and settings