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decode.rar
- LDPC的Verilog程序源代码，包括仿真数据等。文件很大，请慢慢下载,LDPC of Verilog source code, including the simulation data. Large file, please download slowly
uart16550
- uart16550 is a 16550 compatible (mostly) UART core. The bus interface is WISHBONE SoC bus Rev. B. Features all the standard options of the 16550 UART: FIFO based operation, interrupt requests and other. The datasheet can b
UART
- 内含有完整的UART代码，包括发送和接受，且有testbench，可以直接仿真调试-Contain complete UART code, including send and receive and there testbench, can directly Simulation debugging
bpsk2
- 介绍qpsk解调的代码！初学者可以参考参考！比较简单.-Introduction QPSK demodulation code! Beginners can refer to reference! Relatively simple.
ldpc
- 最近在做毕设，ldpc码的编解码实现，这个是verilog实现。-Recently completed the set up to do, ldpc code codec implementation, this is the Verilog implementation.
pll
- 实现同步时采用锁相环，锁相环实现的原理，及源代码，-Implementation of the principle of phase-locked loop, and the source code,
qpsk
- qpsk vhdl code ue to impelemented on fpga kits
ldpcverilog
- verilog编写的ldpc编码的源代码 -ldpc prepared verilog source code
FSK_modulation_and_demodulation
- 模拟数字通信通道，将离散数据利用奇偶效验码编码，FSK调制后，发送，接收端解调解码后还原-Analog-to-digital communication channel, the use of discrete data to be well-tested code parity coding, FSK modulation, the transmission, the receiving end to restore the decoded demodulation
ebook_USB2.0_intel_tranceiver
- High volume USB 2.0 devices will be designed using ASIC technology with embedded USB 2.0 support. For full-speed USB devices the operating frequency was low enough to allow data recovery to be handled in a vendors VHDL code, with the ASIC vendor
chuankoutongxin
- 串口通信的概念非常简单，串口按位（bit）发送和接收字节。尽管比按字节（byte）的并行通信慢，但是串口可以在使用一根线发送数据的同时用另一根线接收数据。它很简单并且能够实现远距离通信。比如IEEE488定义并行通行状态时，规定设备线总常不得超过20米，并且任意两个设备间的长度不得超过2米；而对于串口而言，长度可达1200米。典型地，串口用于ASCII码字符的传输。通信使用3根线完成：（1）地线，（2）发送，（3）接收。由于串口通信是异步的，端口能够在一根线上发送数据同时在另一根线上接收数据。其
RS_Verilog
- RS码的FPGA实现，verilog语言形式，好参考资料-FPGA realization of RS code, verilog language form, a good reference
encode_finish
- Turbo码编码器的encode最上层模块，它的主要作用是连接Turbo码编码器的其他模块-Turbo code encoder encode top-level module, its main role is to connect the Turbo Code encoder other modules
USB2.0code
- 实现USB2.0接口控制的VHDL源代码-USB2.0 VHDL code
CTL_SendTest
- UWB（超宽带）发射端代码控制，主管各个模块的连接和设置-UWB (ultra wideband)-side code to launch control, in charge of connecting the various modules and settings
OFDM
- OFDM是3G的关键技术之一。此代码实现了OFDM的各模块，并附有文档说明OFDM的原理和技术。-OFDM is the key 3G technologies. This code implements the various modules of the OFDM, along with documentation OFDM principles and techniques.
pci-verilog
- USB及PCI总线设计的一些源代码（经测试）-USB and PCI bus design some of the source code
ask
- 通信系统数字信号调制，振幅监控ask信号的调制和解调的VHDL代码-Communication systems digital signal modulation, amplitude control ask signal modulation and demodulation of the VHDL code for
FMreceiver
- FM receiver VHDL code
Booth-Multiplier-VHDL-Code
- 布斯乘法器 Booth Multiplier VHDL Code-Booth Multiplier VHDL Code