搜索资源列表
VGA
- VGA 640x480 controller using FPGA Xilinx using Xilinx ISE 10
CCD
- 本设计主要用来进行图像采集处理，通过摄像头采集图像信息，经过插值算法后存储到外部SDRAM，然后读取图像数据，进行边缘滤波处理后经VGA输出到屏幕上。-This design is mainly used for image acquisition and processing,through the camera capture image information,after interpolation to the external memory after the SDRAM,and th
TanSweeLing
- project mp3 decoder in hardware
BT656
- 此设计主要是完成BT656格式的视频数据的采集(VHDL)-this digital logic design is used to sample the BT656 format frame !
I2S
- 此设计主要是完成音频I2S格式数据流的串并转换和并串转换,用VHDL描述-This design is to complete the audio I2S format data stream serial to parallel conversion and parallel to serial conversion in VHDL
adder
- 基于vhdl硬件描述语言的8位加法器的设计-Based on the design of the 8-bit adder VHDL hardware descr iption language
CD1_OV5620_SAVE_UDP_TRANS
- OV5620 VHDL CODE, Alter FPGA Source Code.
mp3-decoding-VHDL-program
- 完整的MP3解码程序，报告huffman解码，IMDCT,滤波。还附有一些说明-mp3 decode
VD1
- VHDL code of full adder
funciona_con_piezas
- fpga, vhdl i need to his funkin
csa_16
- The folder contains the carry adder code in vhdl. 16 bit adder is designed and coded in vhdl-The folder contains the carry adder code in vhdl. 16 bit adder is designed and coded in vhdl
vhdl
- 音频延迟程序课实现回升功能。。。。。。。。。。。。。20个字？-delay unit
sp6-ov7670
- 包含了用Spartan6控制OV7670的VHDL源程序，以及PC上的测试程序。对于学习EZUSB的朋友很有帮助。-OV7670 includes the use Spartan6 control of VHDL source code, and test program on the PC. EZUSB for learning helpful friends.
Release
- 分解视频的每个像素的RGB信号，主要用于做VHDL仿真的do文件-Each pixel RGB video signal decomposition, mainly used to make VHDL simulation files do
h265enc_v1.0
- 用vhdl语言编写的h.265编码器，可用于xilinx或altera的fpga(h.265 encoder written by vhdl. It can be download to xilinx or altera's fpga)