搜索资源列表
VBuffer_1c6
- 视频采集并锁存到SDRAM中的完整代码，运行环境为QII，VHDL与标准参数宏模块调用混合设计 是学习视频采集的很好的参考-Video Capture SDRAM and latches to the integrity code, the operating environment for QII. VHDL standard parameter-called hybrid module is designed to study the Video Capture good reference
Music
- MAX plus VHDL语言 实现音乐的演奏
mp3_decoder
- 一个用VHDL编写的实现mp3解码功能的代码。This folder contains three directories: Huffman, IMDCT and Filterbank, each of them includes all the VHDL source codes of the component.
continue_wave_radar
- 一个连续波雷达的VHDL实现程序，用VHDL编写，带有测试激励文件
vedio_collection.rar
- 在这个压缩包里，包含了关于视频采集知识的一些基本的介绍。并且在里面还包含了一个基于spartan-3E的视频采集实验,The compressed pack contains some fundemental introdutions about video collections .What s more ,there is a referenced lab on vedio collection which is based on spartan-3E!
mp3decoder.rar
- mp3 解码的verilog代码，通过仿真综合及验证，能够播放所有的.mp3文件。压缩包包括所有的verilog源码以及详细的文档。,mp3 decoding Verilog code, the adoption of an integrated simulation and verification, can all play. mp3 file. Compressed packet including all the Verilog source code and detailed docu
wm8731
- wm8731的使用，用于音频信号的采集或者产生-wm8731 use for audio signal acquisition or produce
TS_control
- MPEG-2 TS 流嵌入控制数据的设计 TS流中的空帧很多，将某些空帧（188字节）全换为控制数据DIN（即在该空帧位置处构成一新的数据帧），按照TS流格式进行传输。TS流数据帧中的数据和控制数据不能出现丢失。-MPEG-2 TS stream control data embedded in the design of TS stream a lot of empty frames, some empty frame (188 bytes) for the control of the
T-REC-H.264-200503-S!!PDF-C
- H.264中文版的翻译，希望对大家有帮助，我从网上找的，发在这里，待阿可以免费下载·-H.264 chinese translation version, wish this can help you in your design and project@
H.264
- 关于h.264视频解码器完全源码（verilog）-With regard to h.264 video decoder full source code (verilog)
hardh264
- 一个硬件H264编码的VHDL源码，用于FPGA开发，适合IP摄像头等视频设备输出数据的编码。用Xilinx工具测试过，但代码不只是用于Xilinx。-A hardware h264 video encoder written in VHDL suited to IP cameras and megapixel cameras. Designed to be synthesized into an FPGA. Initial testing is using Xilinx tools
pro_4d1
- 此代码可实现8bits 108M 4路BT656 像素交织输入转为8bits 108M 4路行交织的视频数据，并有仿真文件，在modelsim中运行即可。-This code can be realized 8bits 108M 4 way BT656 pixel interleaving input into 8bits 108M 4 way line of cutting the video data, and there are simulation files can be run in
auk_ts_input
- ts流输入virilog源码-ts stream input source virilog
nova.tar
- video decoder full hardware
CLK_DIV
- 爱用硬件描述语言VHDL实现输入时钟10分频输出-divide CLOCK by 10 using VHDL
jpeg_latest.tar
- JPEG descr iption by vhdl
simple_fm_receiver.tar
- 一个简单FM接收机的VHDL源码，很有参考意义-A simple FM receiver VHDL source code is very useful
h264buffer
- h.264 program in vhdl
h264components
- it is vhdl program for components used in h.264
h264dctransform2
- it is a vhdl program for dct2 tranform in h.264