搜索资源列表
shipin
- 实现数字化的视频采集与处理系统，以FPGA为处理平台
vga
- 基于FPGA的VGA时序产生/控制器，产生行、场同步时序，并以标准格式输出,并有相应测试代码。开发工具ISE 8.1及以上。-FPGA-based VGA timing generator/controller, resulting in horizontal and vertical sync timing, and a standard format output, and the corresponding test code. Development tool ISE 8.1 and a
hardh264
- 一个硬件H264编码的VHDL源码，用于FPGA开发，适合IP摄像头等视频设备输出数据的编码。用Xilinx工具测试过，但代码不只是用于Xilinx。-A hardware h264 video encoder written in VHDL suited to IP cameras and megapixel cameras. Designed to be synthesized into an FPGA. Initial testing is using Xilinx tools
sram_saa1117verilog
- 图像采集、存储控制verilog源代码，fpga控制SAA1117,采集数据存储到sram，仿真编译测试都能通过-Image acquisition, storage, control verilog source code, fpga control SAA1117, collecting data to sram, simulation tests can be compiled by
FPGA_video
- FPGA 图像采集 资料 论文 比较实用-FPGA system for image sampling,which is very helpful
video_board_schemtic1
- this the schemtic for hooking up a video encoding chip (SAA7121H) to a IDE connector so it can connect to a DE1 FPGA board or any other you fancy-this is the schemtic for hooking up a video encoding chip (SAA7121H) to a IDE connector so it can connec
4
- 采用现场可编程门阵列FPGA实现大部分外围电路，大大提高了数据采集和处理能力-Use of field programmable gate array FPGA to achieve most of the external circuit, greatly improving the data acquisition and processing capabilities
04_PlanAhead
- planahead fpga 设计视频介绍-4-planahead fpga design demo-4
VGA-standrad
- 详细介绍了VGA各个分辨率各帧频的时序标准，在FPGA编程过程中有重要作用-Details the various resolution and frame rate of the VGA timing standards, an important role in the FPGA programming process
CD1_OV5620_SAVE_UDP_TRANS
- OV5620 VHDL CODE, Alter FPGA Source Code.
Face_Detect
- 基于FPGA的视频中的人脸检测算法，亲测可用-FPGA video face detection algorithm, pro-test available
Triple-Rate---DualLink-FPGA-IP-v-2.0-Jul-2008
- Parallel to 5 pair HDSDI encode/decode
PRNG
- 基于FPGA伪随机序列产生器，GOLLMANN级联F-FCSR，产生伪随机序列-FPGA-based pseudo-random sequence generator, GOLLMANN cascade F-FCSR, generating pseudo-random sequence
ROM-MIF
- 利用MATLAB产生FPGA IP 核ROM，初始化文件，用来初始化ROM的MIF文件-Using MATLAB generates FPGA IP Core ROM, initialization files, MIF file is used to initialize the ROM
04_ep2c8_vga_test
- VIP FPGA板的配套例子，这个是VGA格式lcd液晶屏幕显示用。-VIP board supporting example of this is the VGA format PREVIEW.
05_sdram_vga_test
- VIP FPGA板的配套例子，这个是VGA格式lcd液晶屏幕显示用,通过SDRAM。-VIP FPGA board example.
06_sdram_ov7670_rgb_640480
- VIP FPGA板的配套例子，这个是VGA格式lcd液晶屏幕显示用,camera preview。-camera preview for vip board
MT9J003_10M_CMOS_V0.3_SEP13
- MT9J003的设计原理图,基于FPGA驱动,可供开发参考-MT9J003design shcedle ,based on the FPGA driver
rgb2ycrcb
- 颜色空间的转换 由rgb转到ycbcr色域，fpga的源代码程序
Lvds_Receiver
- 基于FPGA实现1080p的LVDS 7:1接收程序(Implementation of 1080p LVDS 7:1 receiving program based on FPGA)