搜索资源列表
multi4_bsdu
- 用VHDL写的4*4乘法器,学习VHDL语言的可以-Use VHDL to write the 4* 4 multiplier, learning VHDL language can be
c16_multiple
- 精通verilog HDL语言编程源码之2--常用乘法器设计-Proficient in verilog HDL source language programming of 2- Common Multiplier
cmult
- 复乘法器的FPGA实现, 希望对初学者有帮助 -Complex Multiplier FPGA to achieve, and they hope to help beginners
csa_float_multiplier
- 新型的浮点乘法器 用csa来实现可以用在浮点乘法器的地方-A new type of floating-point multiplier with CSA to achieve floating-point multiplier can be used in place
Wallace
- 一个关于Wallace树乘法器的论文,当中展示了一种改进后的wallace树乘法器方案,相比原来占用晶体管更少,效率更高-Wallace tree multiplier on the papers, which show an improved wallace tree multiplier after the program, compared to the original transistors occupy less efficient
100vhdl_example
- vhdl语言的100个例子 VHDL语言100例 第1例 带控制端口的加法器 第2例 无控制端口的加法器 第3例 乘法器 第4例 比较器 第5例 二路选择器 第6例 寄存器 第7例 移位寄存器 第8例 综合单元库 第9例 七值逻辑与基本数据类型 第10例 函数 -VHDL language, VHDL language 100 examples of 100 cases of the first one cases of the control p
ps
- RS(204,188)译码器的设计 异步FIFO设计 伪随即序列应用设计 CORDIC数字计算机的设计 CIC的设计 除法器的设计 加罗华域的乘法器设计-RS (204188) decoder design of asynchronous FIFO design application design sequence was pseudo-CORDIC design of digital computer design CIC divider design Le Hua
doc
- VHDL:用状态机的方法实现一个8位乘法器-VHDL: state machine method used to achieve an 8-bit multiplier
multiply
- 由verilog编写的乘法器,通过两个文件的调用实现。由于子模块的调用使得程序简化了许多。-Prepared by the Verilog multiplier, through the realization of the two documents call. As the sub-modules to simplify the procedure call makes a lot.
fir_parall
- 基于verilog的fir滤波器设计,用的并行结构。在前面基础上加入四级流水(加法器,并行乘法器,乘法结果相加两级),通过验证。-Verilog-based design of fir filter using the parallel architecture. In front of the basis of adding four water (adder, parallel multiplier, multiply the result of the sum of two), throu
5438mpy
- msp430单片机最新的产品MSP430F5438内部硬件乘法器的操作的示例程序-MSP430 Product latest single-chip hardware multiplier MSP430F5438 internal operation of the sample programs
VHDL_exmple
- VHDL编程一百例,包括加法器、乘法器、移位寄存器、奇偶校验器等。pdf格式的,仅供学习使用-VHDL Programming 100 cases, including the adder, multiplier, shift register, parity, etc.. pdf format, for learning to use
ff_mul
- 伽勒华域乘法器用于RS编码中,用verilogHDL语言实现-Galle Hua domain multiplier for RS encoding, the implementation language used verilogHDL
ex
- 用HDPLD实现的高速并行乘法器,其输入为两个带符号位的4位二进制数- HDPLD implementation with high-speed parallel multiplier, the input symbols with two 4-bit binary number
Boothmultiplier
- 布斯乘法器的语言描述功能违反外 暗暗达到-Booth multiplier described in the language
Mars_EP1C6F_fundemantal_demo
- FPGA 开发板源码。芯片为Mars EP1C6F.VHDL语言。可实现一些基本的功能。如乘法器、加法器、多路选择器等。-FPGA development board source. Chips for the Mars EP1C6F.VHDL language. Can achieve some of the basic functions. Such as multiplier, adder, such as MUX.
Multiplexer
- 这是一个用vhdl硬件描述语言实现的乘法器而不是多路选择器-this is an implimentation of an multiplier rather than multiplexer.
multi
- 实现了三种乘法器,可以进行性能比较,比较有较之-multi
EPM1270_multiplier
- VHDL 乘法器 源代码,很好的VHDL 入门学习例程序-Multiplier VHDL source code, a good learning example VHDL entry procedures
0
- 用vhdl语言实现4位乘法器,已被测试过,可参考使用-Vhdl language with four multipliers, have been tested, may refer to the use of