搜索资源列表
booth.rar
- 一个基于VerilogHDL语言的16位的booth算法的乘法器及其测试代码,VerilogHDL language based on the 16-bit multiplier of the booth algorithm and test code
add.rar
- 流水线乘法器与加法器 开发环境：Modelsim（verilog hdl）,Multiplier and adder pipeline development environment: Modelsim (verilog hdl)
qfq.rar
- 移位相加乘法器设计。附有工程实例及ppt说明。,Add multiplier design shift. Ppt with example and descr iption.
mux4
- 四位乘法器的VHDL语言设计，并有原理图的描述-4 Multiplier VHDL language design, and schematic descr iption of
MULT
- 乘法器 verilog CPLD EPM1270 源代码-Multiplier verilog CPLDEPM1270 source code
verilog
- verilog语言例题集锦 包含加法器，乘法器，串并转换器等verilog源代码-Example Collection contains verilog language adder, multiplier, and converters, such as string verilog source code
multiplyingunit
- 其乘法器原理是：乘法通过逐项移位相加原理来实现，从被乘数的最低位开始，若为1，则乘数左移后与上一次的和相加；若为0，左移后以全零相加，直至被乘数的最高位-Its multiplier principle is: the sum of multiplication through each shift principle to achieve, from the lowest bit multiplicand to start, if 1, then the multiplier on the l
multiply
- Verilog hdl语言 常用乘法器设计，可使用modelsim进行仿真-Verilog hdl language commonly used multiplier design, can use the ModelSim simulation
add_tree_mult
- 8位加法树乘法器,实现两个8位二进制数相乘，采用verilog hdl-8-bit adder tree multiplier, the achievement of the two 8-bit binary number multiplied, using verilog hdl
booth
- 基于verilog的booth算法的乘法器-Based on the booth algorithm verilog multiplier
mul(FLP)
- 一个32位元的浮点数乘法器，可将两IEEE 754格式的值进行相乘-A 32-bit floating-point multipliers, can be two format IEEE 754 values multiplied
boothmultiplier
- booth算法描述， 8乘8位带符号校验扩展位乘法器-booth algorithm descr iption, 8 x 8 bit multiplier with symbol check extension
multiplexer
- 几种常用乘法器的Verilog、VHDL代码-Several common multiplier Verilog, VHDL code
61EDA_D721
- 8*8乘法器设计，和大家共享，互相学习，共同进步-8* 8 multiplier design, and for all to share and learn from each other and progress together
32-bit_multiplier_model
- 此程序为32-bit乘法器，另附有VHDL测试程序-This procedure for 32-bit multiplier, followed VHDL test procedures
multi16
- verilog 写的两种方式的乘法器 不错!-Verilog write the multiplier in two ways good!
Pentium
- 这两个分别是8位乘法器的VHDL语言的实现，并经过个人用QUARTUS的验证，另外一个是奔腾处理器的设计思想-The two were 8 multiplier realization of VHDL language and personal use Quartus After verification, another is a Pentium processor design idea
chengfaqi4
- 用VHDL实现四位乘法器，不直接用乘法实现，一来节省资源，二来可提高速度！-Use VHDL to achieve four multiplier, not the realization of the direct use of multiplication, one to save resources, and secondly to improve the speed!
GFmultiply
- Verilog hdl语言 伽罗华域GF（q）乘法器设计，可使用modelsim进行仿真-Language Verilog hdl Galois field GF (q) multiplier design, can use the ModelSim simulation
serial_multiplex
- 绝对好东西，一个VHDL写的任意宽度通用串行乘法器，以最少的资源实现乘法器功能。-Definitely a good thing, a VHDL to write arbitrary width universal serial multiplier, the least amount of resources to achieve multiplier function.