搜索资源列表
rc6_avr
- AVR单片机的优化RC6 加密算法(速度快,其优化思想绝对值得学习) 在有128bytes RAM 的AVR单片机上执行 rc6 16/10/8(16 bit/10 rounds/8 bytes keys) * 对多数代码进行了 C 语言优化,对数据相关循环移位,模乘等用ASM优化 * 在4MHz无乘法器的AVR上得到平均 1172 Bytes/s的加解密速度。 * 编译器: AVR-G-AVR optimization RC6 encryption algorithm
VHDL语言写的简易计算器
- 用VHDL写的简易计算器,包括加减乘除,除法器用加法器和乘法器组成-Write simple calculator with VHDL, division, including add, subtract, multiply and divide adder on time-multiplier and used
VHDL
- 本代码为用VHDL语言设计实现加法器、减法器、乘法器,并提供了模块图,进行了波形仿真。-This code is for the use of VHDL Language Design and Implementation of adder, subtracter, multiplier, and provides a block diagram carried out a wave simulation.
mltiply_machine
- verilog语言写的乘法器,每一步经过验证,毫发无损,拿出来与大家共享,在quartus II 上编程,仿真在cyclone 2上!!谢谢!-written multiplier verilog language, every step of the proven, intact, and show to share the quartus II on programming, simulation in cyclone 2 on! ! Thank you!
pipe_mul8
- verilog实现的流水线8位乘法器,效率高,代码简洁经典-verilog implementation of pipelined 8-bit multiplier, efficient, simple and classic code
Multipliers
- 各种乘法器,不同算法类型的,适用于不同情况。(Various multipliers, different algorithmic types, are applied to different situations.)
original_code_multiplier
- 16位原码乘法器,附带测试程序,实现两个16位的乘数相乘。(16-bit original code multiplier with test program)
unsigned_array_multiplier
- 4X4位的无符号型阵列乘法器,可以提高乘法的运算速度(4X4 bit unsigned array multiplier, can increase the multiplication of the operation speed)
mul8
- 用verilog设计了一个两个8位二进制数的乘法器(A multiplier of two 8 bit binary numbers is designed with Verilog)
16bit-multiplier
- 实现verilog16位乘法器,verilog新手(achieve 16-bit multiplier)
17
- CSD实现一个乘法器,是一个十一位乘以十七的乘法器,可用于滤波器的相关乘法器设计。(CSD implements a multiplie)
16 bit signed number multiplier
- 16位有符号数乘法器,使用Booth编码和华莱士树,提供程序源文件和测试文件(The 16 bit signed multiplier uses Booth encoding and Wallace tree to provide source files and test files.)
mux16
- 基于quartus的FPGA乘法器Verilog程序(FPGA multiplier program based on quartus)
float_mult32x32.v
- verilog 语言写的FPGA内部实现硬件浮点乘法器的源码,两个时钟周期完成一次浮点乘法运算(The FPGA language written in Verilog implements the source of the hardware floating point multiplier, and completes the floating point multiplication operation in two clock cycles.)
multiplication
- 在FPGA里面实现了多位乘法器的功能,并用modelsim进行了仿真,还对该乘法器进行了优化(The function of multi-bit multiplier is realized in the FPGA, and it is simulated with modelsim, and the multiplier is optimized)
multi
- 基于Verilog HDL 的乘法器,可以实现一些功能的计算(Multiplier based on Verilog HDL)
multiplier
- Booth乘法器是属于位操作乘法器,采用流水线结构实现(The Booth multiplier is a bit-operated multiplier that is implemented in a pipeline structure.)
矩阵乘法器
- 基于乘法器ip核实现的矩阵乘法器,最大支持16*16的矩阵,基于VHDL编写,仅支持整数,浮点数类型请自行添加浮点数IP核支持。
乘法器testbench
- 用于相关四位二进制乘法的简单乘法器仿真使用的testbench