搜索资源列表
mul
- 八位乘法器的VHDL程序,按照乘法的运算规则利用分支语句判断所有情况,最后累加求的结果-8 multiplier VHDL programs, in accordance with rules of multiplication operations to determine all the circumstances of the use of a branch statement, the final cumulative result of demand
mult16s
- 16位乘法器,VHDL语言编写的,供大学交流学习-16-bit multiplier
8-bit
- 最基本的vhdl運算,採用8bit作乘法器,將兩串8bit的值輸入之後進行相乘-VHDL basic computing, the use of 8bit for the multiplier, will be the value of two strings of 8bit input multiplied after
GFverilog-hdl
- 伽罗华域的乘法器的设计,使用有限域设计乘法器-Galois field multiplier design, the use of finite field multiplier design
fft
- 基于VHDL语言编写的FFT程序,256点,旋转因子存在自己编写的ROM里面,乘法器和数据存储采用的是IP核-FFT-based program written in VHDL, 256 points, there is rotation factor which I have written the ROM, multiplier, and data storage is used in IP core
FPGA-basedmultipliersCSDcode
- 基于FPGA的CSD编码乘法器(在MATLAB环境中)-FPGA-based multipliers CSD code (in MATLAB environment)
Hardware_Multiplier
- 用VHDL写的硬件乘法器,以及测试过了,一个时钟周期内完成乘法运算。被乘数、乘数的宽度通过通用属性GENERIC参数改变而轻松改变,硬件除法器也快好了。-Written by VHDL hardware multiplier, and tested, and a clock cycle multiplication. Multiplicand, multiplier width parameter changes through the common property of GENERIC an
Mul_16
- 16位布思乘法器,实现两个16位二进制相乘,运行runallcode.bat文件可自动生成fsdb波形文件观察结果-16bits-multibly-16bits buth mutiplayer
32_bit_complex_multiplier
- 一款32位复数乘法器,用verilog写的。-32_bit complex multiplier,written in verilog HDL.
Booth_mul4_v
- 四位BOOTH乘法器 Booth算法(布斯算法),一个比较推荐的带符号乘法算法-Booth_mul4
mult16
- 基于wallance树的16位乘法器,程序是用verilog写的,经测试好用,对初学者有很大的帮助-16-bit multiplier, based on wallance tree program is written with verilog test handy for beginners great help
array_multiplier
- 4X4阵列乘法器,图可以按程序画看看,可以改进-4X4 array multiplier, see Figure can draw according to the procedure can improve
verilog-example
- 4位并行乘法器 4位超前加法器 ALU 计数器 滤波器 全加器 序列检测器 移位器-failed to translate
ddsVHDL
- fpga实例 包含很多使用的例子 累加器 乘法器 触发器等-FPGA example real Verilog HDL
Chapter6-9
- 第六章到第九章的代码 本书通过100多个模块实例,详细地讲解了Verilog HDL程序设计语言,全书共分13章,内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等,实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例
mul
- 定点乘法器的FPGA仿真,对于学习硬件设计的朋友应该有帮助-Fixed-point multiplier FPGA simulation, hardware design for the study should help a friend
CCMU
- 代码是一个复数乘法器,两个复数相乘,只用到了2个实数相乘,运算量少-Code is a complex multiplier, two complex multiplication, uses only real number multiplied by 2, operations less
cmultip
- 用VERILOG HDL 实现节省乘法器的16位复数乘法器-With VERILOG HDL achieve savings of 16-bit complex multiplier multiplier
EDA
- 移位相加8位硬件乘法器电路设计,该乘法器是由8位加法器构成的以时序方式设计的8位乘法器。-Add 8-bit hardware multiplier shift circuit design, the multiplier is composed of 8-bit adder to temporal order, 8-bit multiplier design.
ls12_mux16
- 一个16位乘法器的veriolog语言实现。使用初学着。-A 16-bit multiplier veriolog language. Use a novice.