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51单片机简易两位计算器全套
- 交学校的作业,包括原程序,仿真电路,论文.
用VHDL编写的带报错和暂停控制功能的 交通灯
- 现代数字系统作业 在maxplus 10.0中调试通过
VHDL 编程
- 包含源代码
work.rar
- 上载的内容为随机信号处理的作业,具体是:其中W(t)为均值为零,方差为3的白噪声。 (1)产生若干组500个点长随机序列。 (2)找一个ARMA模型与(1)中的500个点匹配。 (3)在产生一个500个点长的随机序列校正。 ,Upload the contents of random signal processing operations, specifically: one of W (t) for the mean zero, variance of white noise for
CH4.rar
- 本文设计的用单片微机控制的甲烷浓度报警监控仪,是采用热催化原理(俗称黑白元件)探头制成的甲烷浓度测量仪,适用于中小型煤矿井下各作业场所中测量空气中的甲烷浓度。基于单片机控制的甲烷浓度监控报警仪。,In this paper, the design of computer control using a single concentration of the methane monitor alarm is hot catalytic principle (commonly known as bl
tsinghuaembeded.rar
- 清华嵌入式系统作业,lpc2124+lcd+串口+ucos,Tsinghua embedded system operation, lpc2124+ lcd+ Serial+ ucos
MIPS
- 组成原理大作业--基于MIPS的运算器设计,内附详细设计文档,包含设计文档和使用手册,主程序,测试程序,还有设计的框图等。实现了可以执行基本的MIPS有关运算器相关的指令共17条,用Verilog编写。-Composition Principle big operation- based on the MIPS computing design, containing a detailed design document, including design documentation and u
dsp
- 一次dsp作业的答案,主要的目的是仿真自适应滤波器中自适应陷波器的算法-adaptive filter ——》wave trap
project2_verilog
- 简化LAPS协议实现,verilog的大作业。-Simplify the LAPS protocol, verilog great job.
lapsa
- 这是清华大学电子系的一个课程作业,要求学生用VHDL实现LAPSA协议。-This is the Department of Electronics, Tsinghua University, one course of operation, require students to achieve LAPSA agreement with VHDL.
verilog
- 一个可以综合的Verilog 7段秒表实例。上海交大微电子学院课程作业。-An example Verilog project. 7-segment
code
- 清华大学《嵌入式操作系统》课程实践的小作业和大作业,仅供才考。-just as reference
MIPS
- MIPS处理器的组员大作业,可以直接运行,提交,环境是quartus-MIPS processor crew great job, you can run directly, the author, the environment is quartusII
Assignment
- DSP课程的作业,显示低通巴特沃斯滤波器的滤波效果。代码和仿真图已经给出。-DSP course work, low-pass Butterworth filter shows the filter effect. Code and simulation map has been given.
wentingDsP
- DSP培训 作业【源码】 -DSP training operations [Source]
bingfanghujiao
- 单片机51,C语言,病房呼叫系统,课程设计作业,希望对有些人有帮做-Single-chip 51, C language, ward call system, curriculum design operation, in the hope that some people have done to help
4bit_buma_adder
- Verilog作业 :自己写的源码输入,补码输出的,由状态机控制的四位加法器,为保证时序,加法器模块为超前近位加法器,包含测试台,通过 Modelsim 、Synplify仿真。-Verilog operation: the source code to write their own input, complementary code output by the state machine to control the four adder, in order to ensure timing
verilog
- 组成原理的大作业,写一个计算器,用verilog语言写的-The composition of the major principles of operation, write a calculator, using the language written in Verilog
LIU
- 人员报警系统,采用51单片机为控制器,用在船舶运输工具上,为人员的危险地段作业,特意设置的,分别采用5分钟,10分钟,15分钟,25分钟,等等时间作业,当作业人员遇到到危险时,就报警,让外部人员知道,做及时的救援,并且采用两组电源检查,希望能给需要帮组的人提供参考-Staff alarm system, using 51 single-chip for the controller, means of transport used in ships for the personnel opera