搜索资源列表
1sfrequency
- 51单片机用1s的周期测信号源频率八位数码管显示-51 MCU 1s cycle measured source frequency eight digital display
ad9850
- 基于ad9850DDS芯片的宽频信号源的并行程序-Based on the chips broadband signal source ad9850DDS parallel program
WTE_Cpe
- libwindos下的虚拟意义设计，，有频谱仪和示波器，信号源驱动应用-libwindos under virtual sense design, spectrum analyzer and oscilloscope, signal source drive applications
wte_dsp
- 虚拟仪器自动校准测试，，包含示波器，，频谱仪，，信号源，功率计等-Automatic calibration test of virtual instruments, including oscilloscopes, spectrum analyzer, signal source, power meter, etc.
DDS_total
- quartus下的DDS信号源设计，可实现多种波形不同频率和幅度的切换，人机界面友好。-design the quartus under the DDS source, can achieve a variety of waveforms of different frequencies and amplitude switching, friendly interface.
dds_quicklogic-FPGA
- dds_quicklogic FPGA DDS信号源-dds_quicklogic FPGA
souce
- 由c80581f410产生的信号源用于和功放同时使用-c8051f410 produce singnal
dpsk_3rd
- 2DPSK调制与解调。学生实验使用，包括信号源模块、时钟源生成模块、信号调制模块，信号解调模块。 其中包含了边沿触发下的阻塞语句。 编译环境：Q2 11.0，编译语言：verilog，仿真软件：moelsim altera -2DPSK modulation and demodulation. The student experiments, including the source module clock source generation module, signal modu
shuzizhong
- 无编程纯属硬件实现数字钟功能信号源用555定时器390双十进制计数器4511数码管驱动-No programming purely hardware implementation of a digital clock function source digital tube driver with 555 timer 390 pairs of decimal counter 4511
shudian
- DDS信号源设计，通过频率控制字k可以自动调节波形频率的输出-DDS signal source design, frequency control word k can automatically adjust the frequency of the waveform output
DDS_PIC
- 用PIC单片机实现的控制AD9851芯片做的DDS信号源，代码可供测试，完全可行。-To do with the PIC MCU control AD9851 chip DDS source code available for testing, entirely feasible.
cmi
- 运用4阶m序列产生信号源 即消息码 用verilog编程实现cmi的产生-The use of fourth-order m-sequence generator source message code Verilog programming cmi generation
DDS_SYS_CLK100M
- 基于FPGA的信号源设计，100M时钟，32位相位累加，能产生正玄波、方波，三角波，锯齿波，频率可调，频率范围0.03HZ-15MHZ。-FPGA-based signal source design, 100M clock, 32-bit phase accumulation can produce sine wave, square wave, triangle wave, sawtooth, adjustable frequency, the frequency range 0.03 Hz
VHDL-DDS
- 基于FPGA的DDS信号源设计，32位相位累加器，产生可调频率-FPGA-based DDS signal source design, 32-bit phase accumulator to generate tunable frequency
DDS_dac9764
- verilog语言编写的DDS信号源，采用DAC9764-verilog DDS signal source language, using DAC9764
reg8b
- 8位寄存器设计，用VHDL语言编写，用于DDS信号源中项目-8 registers design using VHDL language for DDS signal source project
adder16b
- 16位寄存器设计，用VHDL语言编写，用于DDS信号源中项目-16 registers design using VHDL language for DDS signal source project
sanjiaobo
- DDS信号源中关于三角波的设计，程序上采用VHDL编写，结果仿真通过-DDS signal source on the triangle wave design, procedural preparation of VHDL simulation results through
sin
- DDS信号源设计中关于正弦信号的波形发生器，采用VHDL编写完-DDS signal source design on the sinusoidal signal waveform generator, using VHDL prepared END
DDS
- DDS信号源实现源码，实现正弦波、方波、三角波等，频率、相位可调。-DDS signal source to achieve source