搜索资源列表
卷积码、CRC
- 卷积码的C源程序,包括编码器和译码器。 还有一个是循环荣誉校验的vhdl]源码。-convolution of C source code, including the encoder and decoder. There is a cycle of the calibration honor VHDL] source.
gsmch
- gsm的卷积码编码和viterbi译码的源码-gsm convolution encoder and Viterbi decoding FOSS
viterbidecoder
- 提供实现了(2,1,7)卷积码的维特比译码的源程序,采用了最大似然算法,介绍了软判决维特比译码算法过程的三个步骤:初始化、度量更新和回溯译码。-for achieving a (2,1,7) Convolutional Codes Viterbi decoding of the source, using the maximum - likelihood algorithm, introduced a soft-decision Viterbi decoding algorithm of the
Viterbi
- (2,1,3)卷积码的Viterbi译码C程序,已经验证成功
viterbi
- 卷积码编码及其Viterbi译码的实现
(2,1,3)卷积码编解码
- (2,1,3)卷积码编解码,viterbi译码
convolution_encoder_VHDL
- 卷积码编译码,由SERVICE、PSDU、TAIL和PAD域组成的DATA域应进行卷积编码,码率应根据所需的传输速率从R=1/2,2/3,3/4中选择-for 802.11a simulation WLAN FEC convolution_encoder g0=133 g1=171 Rate 0:1/2 1:2/3 2:3/4 for 802.11a simulation
viterbi
- verilog程序,实现了(2,1,4)卷积码编码,和基于回溯算法的维特比译码器-verilog program to achieve the (2,1,4) convolutional code encoding, and algorithm based on the back of the Viterbi decoder
ViterbiDecodeK9R12HardDecision
- viterbi 硬判决译码,基本实现了(2,1,9)卷积码的硬判决译码,用modelsim RTL仿真通过-hard-decision viterbi decoding, the basic realization of the (2,1,9) convolutional codes hard decision decoding, using modelsim RTL simulation through
115157715conv_code
- FPGA实现卷积码的功能 是一个卷积码的编译码过程实现 -FPGA realization of the function of convolutional codes
mywork1
- 卷积码的viterbi译码,用Visual dsp 开发-viterbi
viterbidecoder
- viterbi译码器的Verilog实现,(3,1,7)零尾卷积码-viterbi decoder implementation by verilog HDL (3,1,7)zero tail conventional code
convolutional_code
- 卷积码编码,经过模拟的有噪信道,viterbi译码,汇编实现-Convolutional coding, through the simulation of noisy channel, viterbi decoding, compiling achieve
viterbi
- 有关信号处理方面的源代码,卷积码的维特比译码函数-failed to translate
UHF-RFID-CRC
- 本文首先研究了IsO/IECl8000.6标准中A、B两类短程通讯的前向链路与返回 链路的数据编码方式,对(FMO)双相间隔编码、(PIE)脉冲间隔编码、曼切斯特码 的编解码方式和技术参数进行了深入的分析,并利用FPGA实验平台对这三种编 码的编、解码电路进行了设计和仿真。然后对UHF RFID系统的差错控制技术原理 进行了探讨,重点研究了ISo/IECl8000.6标准中采用的数据保护与校验技术,即 循环冗余校验(CRC)技术。分析了基于线性反馈移位寄存器(LFSR)实现C
Viterbi_verilog
- 在ISE环境下用Verilog语言编写的卷积码程序及Viterbi译码程序-Under the ISE Verilog language with procedures and Viterbi convolutional code decoding program
viterbi
- 高效率的viterbi译码,对通信中的卷积码进行译码-Efficient viterbi decoding of communications for decoding convolutional codes
finial_test
- 卷积码和Viterbi译码的源程序,在Xilinx ISE环境下使用Verilog编写,有助于卷积码和Viterbi译码的学习-Convolutional codes and Viterbi decoding of the source, in the Xilinx ISE environment, use of Verilog prepared to help convolutional codes and Viterbi decoding of the study
卷积码、CRC
- 卷积码的C源程序,包括编码器和译码器。还有一个是循环荣誉校验的vhdl]源码。-convolution of C source code, including the encoder and decoder. There is a cycle of the calibration honor VHDL] source.
(2,1,3)卷积编码和viterbi译码
- 自己写的(2,1,3)卷积编码器和viterbi译码,测试已通过